[llvm] 0d237d1 - [RISCV] Merge rv32/rv64 test files. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 12:19:31 PDT 2022
Author: Craig Topper
Date: 2022-04-06T12:18:45-07:00
New Revision: 0d237d1f055d307439785be8a173f7b81e9aaffe
URL: https://github.com/llvm/llvm-project/commit/0d237d1f055d307439785be8a173f7b81e9aaffe
DIFF: https://github.com/llvm/llvm-project/commit/0d237d1f055d307439785be8a173f7b81e9aaffe.diff
LOG: [RISCV] Merge rv32/rv64 test files. NFC
Added:
llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
Modified:
Removed:
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
deleted file mode 100644
index 56f6577de38e1..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
+++ /dev/null
@@ -1,2529 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
-
-; FIXME: The scalar/vector operations ('fv' tests) should swap operands and
-; condition codes accordingly in order to generate a 'vf' instruction.
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oeq_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ogt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oge_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_olt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ole_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_one_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmflt.vv v13, v10, v8
-; CHECK-NEXT: vmor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_one_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_one_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmflt.vf v11, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_one_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v12, v10, v10
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v12, v10, v10
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmflt.vv v13, v10, v8
-; CHECK-NEXT: vmnor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmflt.vf v11, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v12, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v12, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v12, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v10, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_une_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_une_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_une_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v12, v10, v10
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x half> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v12, v10, v10
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x half> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
- %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x half> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_oeq_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ogt_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_oge_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_olt_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ole_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_one_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v16, v8, v12
-; CHECK-NEXT: vmflt.vv v17, v12, v8
-; CHECK-NEXT: vmor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_one_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v12, v8, fa0
-; CHECK-NEXT: vmfgt.vf v13, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_one_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v12, v8, fa0
-; CHECK-NEXT: vmflt.vf v13, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_one_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_one_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v16, v12, v12
-; CHECK-NEXT: vmfeq.vv v12, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v16
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfeq.vf v16, v12, fa0
-; CHECK-NEXT: vmfeq.vv v12, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ord_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfeq.vf v16, v12, fa0
-; CHECK-NEXT: vmfeq.vv v12, v8, v8
-; CHECK-NEXT: vmand.mm v0, v16, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v16, v12, v12
-; CHECK-NEXT: vmfeq.vv v12, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v16
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfeq.vf v16, v12, fa0
-; CHECK-NEXT: vmfeq.vv v12, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v16, v8, v12
-; CHECK-NEXT: vmflt.vv v17, v12, v8
-; CHECK-NEXT: vmnor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v12, v8, fa0
-; CHECK-NEXT: vmfgt.vf v13, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ueq_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v12, v8, fa0
-; CHECK-NEXT: vmflt.vf v13, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v13, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v16, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ugt_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v16, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_uge_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v16, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ult_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v16, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_ule_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v12, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v12, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_une_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_une_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_une_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_une_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_une_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v16, v12, v12
-; CHECK-NEXT: vmfne.vv v12, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v16
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfne.vf v16, v12, fa0
-; CHECK-NEXT: vmfne.vv v12, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
-; CHECK-LABEL: fcmp_uno_fv_nxv8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfne.vf v16, v12, fa0
-; CHECK-NEXT: vmfne.vv v12, v8, v8
-; CHECK-NEXT: vmor.mm v0, v16, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x float> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v16, v12, v12
-; CHECK-NEXT: vmfne.vv v12, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v16
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x float> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32_nonans(<vscale x 8 x float> %va, float %b) #0 {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vmfne.vf v16, v12, fa0
-; CHECK-NEXT: vmfne.vv v12, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
- %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x float> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_oeq_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oeq <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ogt_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp ogt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ogt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_oge_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp oge <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp oge <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_olt_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp olt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp olt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ole_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp ole <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ole <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_one_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v24, v8, v16
-; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vmor.mm v0, v25, v24
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_one_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v16, v8, fa0
-; CHECK-NEXT: vmfgt.vf v17, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_one_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v16, v8, fa0
-; CHECK-NEXT: vmflt.vf v17, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_one_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp one <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_one_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp one <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: vmfeq.vv v16, v8, v8
-; CHECK-NEXT: vmand.mm v0, v16, v24
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v24, v16, fa0
-; CHECK-NEXT: vmfeq.vv v16, v8, v8
-; CHECK-NEXT: vmand.mm v0, v16, v24
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ord_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v24, v16, fa0
-; CHECK-NEXT: vmfeq.vv v16, v8, v8
-; CHECK-NEXT: vmand.mm v0, v24, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: vmfeq.vv v16, v8, v8
-; CHECK-NEXT: vmand.mm v0, v16, v24
-; CHECK-NEXT: ret
- %vc = fcmp ord <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v24, v16, fa0
-; CHECK-NEXT: vmfeq.vv v16, v8, v8
-; CHECK-NEXT: vmand.mm v0, v16, v24
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ord <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v24, v8, v16
-; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vmnor.mm v0, v25, v24
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v16, v8, fa0
-; CHECK-NEXT: vmfgt.vf v17, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ueq_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v16, v8, fa0
-; CHECK-NEXT: vmflt.vf v17, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v17, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp ueq <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ueq <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v24, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v24, v24
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ugt_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp ugt <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ugt <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v24, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v24, v24
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_uge_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = fcmp uge <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uge <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v24, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v24, v24
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ult_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp ult <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ult <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v24, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v24, v24
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_ule_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v16, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v16, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp ule <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp ule <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_une_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_une_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_une_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_une_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = fcmp une <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_une_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_une_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp une <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v24, v16, v16
-; CHECK-NEXT: vmfne.vv v16, v8, v8
-; CHECK-NEXT: vmor.mm v0, v16, v24
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v24, v16, fa0
-; CHECK-NEXT: vmfne.vv v16, v8, v8
-; CHECK-NEXT: vmor.mm v0, v16, v24
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
-; CHECK-LABEL: fcmp_uno_fv_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v24, v16, fa0
-; CHECK-NEXT: vmfne.vv v16, v8, v8
-; CHECK-NEXT: vmor.mm v0, v24, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x double> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v24, v16, v16
-; CHECK-NEXT: vmfne.vv v16, v8, v8
-; CHECK-NEXT: vmor.mm v0, v16, v24
-; CHECK-NEXT: ret
- %vc = fcmp uno <vscale x 8 x double> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64_nonans(<vscale x 8 x double> %va, double %b) #0 {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f64_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v24, v16, fa0
-; CHECK-NEXT: vmfne.vv v16, v8, v8
-; CHECK-NEXT: vmor.mm v0, v16, v24
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
- %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
- %vc = fcmp uno <vscale x 8 x double> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
-; node. Ensure we correctly (custom) lower this.
-define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
-; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.d.x ft0, zero
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v24, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: add a1, a0, a0
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v24, a0
-; CHECK-NEXT: ret
- %vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
- ret <vscale x 16 x i1> %vc
-}
-
-attributes #0 = { "no-nans-fp-math"="true" }
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
similarity index 98%
rename from llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
index 1e94ca2e2d545..b243ecc5f4b0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; FIXME: The scalar/vector operations ('fv' tests) should swap operands and
; condition codes accordingly in order to generate a 'vf' instruction.
@@ -2510,18 +2512,31 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64_nonans(<vscale x 8 x double> %va,
; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
; node. Ensure we correctly (custom) lower this.
define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
-; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.d.w ft0, zero
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v24, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: add a1, a0, a0
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v24, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: fcmp_oeq_vf_nx16f64:
+; RV32: # %bb.0:
+; RV32-NEXT: fcvt.d.w ft0, zero
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: vmfeq.vf v24, v16, ft0
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: srli a0, a0, 3
+; RV32-NEXT: add a1, a0, a0
+; RV32-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
+; RV32-NEXT: vslideup.vx v0, v24, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: fcmp_oeq_vf_nx16f64:
+; RV64: # %bb.0:
+; RV64-NEXT: fmv.d.x ft0, zero
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV64-NEXT: vmfeq.vf v24, v16, ft0
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: srli a0, a0, 3
+; RV64-NEXT: add a1, a0, a0
+; RV64-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
+; RV64-NEXT: vslideup.vx v0, v24, a0
+; RV64-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
deleted file mode 100644
index 6e86aaa4b7257..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
+++ /dev/null
@@ -1,2960 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
-
-define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_eq_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp eq <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_eq_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_eq_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmseq.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_eq_iv_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_ne_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp ne <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ne_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsne.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ne_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsne.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ne_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_ugt_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %vc = icmp ugt <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ugt_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v9
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_uge_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %vc = icmp uge <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_uge_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_uge_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v9
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, -16
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 14
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_iv_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-; Test that we don't optimize uge x, 0 -> ugt x, -1
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i64 %vl) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i64 %vl)
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_ult_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp ult <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ult_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ult_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_iv_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmclr.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8>, i8, i64);
-
-; Test that we don't optimize ult x, 0 -> ule x, -1
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i64 %vl) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, zero
-; CHECK-NEXT: ret
- %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i64 %vl)
- %vc = icmp ult <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_ule_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp ule <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ule_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_ule_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_ule_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_sgt_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v9, v8
-; CHECK-NEXT: ret
- %vc = icmp sgt <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sgt_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v9
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_sge_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v9, v8
-; CHECK-NEXT: ret
- %vc = icmp sge <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sge_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsle.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sge_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v9
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, -16
-; CHECK-NEXT: vmsle.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -1
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_slt_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp slt <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_slt_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_slt_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, zero
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
-; CHECK-LABEL: icmp_sle_vv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v8, v9
-; CHECK-NEXT: ret
- %vc = icmp sle <vscale x 8 x i8> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sle_vx_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
-; CHECK-LABEL: icmp_sle_xv_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsle.vv v0, v9, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i8> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: icmp_sle_vi_nxv8i8_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_eq_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp eq <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_eq_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_eq_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmseq.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_eq_iv_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_ne_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp ne <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ne_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsne.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ne_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsne.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ne_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_ugt_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = icmp ugt <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ugt_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_uge_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = icmp uge <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_uge_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsleu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_uge_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v10, -16
-; CHECK-NEXT: vmsleu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 14
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_iv_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_ult_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp ult <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ult_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ult_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_iv_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmclr.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i16_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_ule_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp ule <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ule_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_ule_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsleu.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_ule_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_sgt_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = icmp sgt <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sgt_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_sge_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %vc = icmp sge <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sge_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sge_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v10
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v10, -16
-; CHECK-NEXT: vmsle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -1
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_slt_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp slt <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_slt_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_slt_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, zero
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
-; CHECK-LABEL: icmp_sle_vv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v8, v10
-; CHECK-NEXT: ret
- %vc = icmp sle <vscale x 8 x i16> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sle_vx_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
-; CHECK-LABEL: icmp_sle_xv_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsle.vv v0, v10, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i16> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: icmp_sle_vi_nxv8i16_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_eq_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp eq <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_eq_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_eq_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmseq.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_eq_iv_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_ne_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp ne <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ne_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsne.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ne_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsne.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ne_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_ugt_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = icmp ugt <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ugt_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_uge_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = icmp uge <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_uge_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsleu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_uge_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v12, -16
-; CHECK-NEXT: vmsleu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 14
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_iv_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_ult_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp ult <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ult_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ult_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_iv_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmclr.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i32_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_ule_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp ule <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ule_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_ule_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsleu.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_ule_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_sgt_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = icmp sgt <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sgt_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_sge_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %vc = icmp sge <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sge_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sge_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v12
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v12, -16
-; CHECK-NEXT: vmsle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -1
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_slt_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp slt <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_slt_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_slt_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, zero
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
-; CHECK-LABEL: icmp_sle_vv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v8, v12
-; CHECK-NEXT: ret
- %vc = icmp sle <vscale x 8 x i32> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sle_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: icmp_sle_xv_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsle.vv v0, v12, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i32> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: icmp_sle_vi_nxv8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_eq_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp eq <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_eq_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_eq_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmseq.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_eq_vi_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_eq_iv_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp eq <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_ne_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsne.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp ne <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ne_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsne.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ne_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsne.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ne_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ne <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_ugt_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = icmp ugt <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ugt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ugt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ugt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_uge_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = icmp uge <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_uge_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_uge_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.i v16, -16
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 14
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_iv_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp uge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_ult_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsltu.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp ult <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ult_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ult_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsltu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsltu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_iv_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgtu.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmclr.m v0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i64_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ult <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_ule_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp ule <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ule_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ule_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_ule_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsleu.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp ule <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_sgt_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = icmp sgt <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sgt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sgt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sgt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_sge_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %vc = icmp sge <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sge_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sge_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.i v16, -16
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -1
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sge <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_slt_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmslt.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp slt <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_slt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_slt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmslt.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -16
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, -16
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsgt.vi v0, v8, -15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmslt.vx v0, v8, zero
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 15
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp slt <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
-; CHECK-LABEL: icmp_sle_vv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vv v0, v8, v16
-; CHECK-NEXT: ret
- %vc = icmp sle <vscale x 8 x i64> %va, %vb
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sle_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vx v0, v8, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sle_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i64> %splat, %va
- ret <vscale x 8 x i1> %vc
-}
-
-define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: icmp_sle_vi_nxv8i64_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmsle.vi v0, v8, 5
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
- %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
- %vc = icmp sle <vscale x 8 x i64> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
-; This icmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
-; node. Ensure we correctly (custom) lower this.
-define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) {
-; CHECK-LABEL: icmp_eq_vi_nx16i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: add a1, a0, a0
-; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v24, v16, 0
-; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v24, a0
-; CHECK-NEXT: ret
- %vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer
- ret <vscale x 16 x i1> %vc
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
index fe0e8acb0e595..64ae9cdd0e19a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
@@ -1,5 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_eq_vv_nxv8i8:
@@ -287,6 +290,20 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
ret <vscale x 8 x i1> %vc
}
+; Test that we don't optimize uge x, 0 -> ugt x, -1
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, iXLen %vl) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
+; CHECK-NEXT: ret
+ %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl)
+ %vc = icmp uge <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i1> %vc
+}
+
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_ult_vv_nxv8i8:
; CHECK: # %bb.0:
@@ -395,16 +412,16 @@ define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
ret <vscale x 8 x i1> %vc
}
-declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8>, i8, i32);
+declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8>, i8, iXLen);
; Test that we don't optimize ult x, 0 -> ule x, -1
-define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i32 %vl) {
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, iXLen %vl) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v0, v8, zero
; CHECK-NEXT: ret
- %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i32 %vl)
+ %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl)
%vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc
}
@@ -1029,20 +1046,6 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
ret <vscale x 8 x i1> %vc
}
-; Test that we don't optimize uge x, 0 -> ugt x, -1
-define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i32 %vl) {
-; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v9, v8
-; CHECK-NEXT: ret
- %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i32 %vl)
- %vc = icmp uge <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i1> %vc
-}
-
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: icmp_ult_vv_nxv8i16:
; CHECK: # %bb.0:
@@ -2224,18 +2227,24 @@ define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
}
define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_eq_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmseq.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_eq_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmseq.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_eq_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmseq.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp eq <vscale x 8 x i64> %va, %splat
@@ -2243,18 +2252,25 @@ define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_eq_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmseq.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_eq_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmseq.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_eq_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmseq.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp eq <vscale x 8 x i64> %splat, %va
@@ -2308,18 +2324,24 @@ define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
}
define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ne_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsne.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ne_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsne.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ne_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsne.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ne <vscale x 8 x i64> %va, %splat
@@ -2327,18 +2349,25 @@ define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ne_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsne.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ne_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsne.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ne_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsne.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ne <vscale x 8 x i64> %splat, %va
@@ -2368,18 +2397,24 @@ define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ugt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ugt_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsltu.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ugt_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ugt <vscale x 8 x i64> %va, %splat
@@ -2387,18 +2422,25 @@ define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ugt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ugt_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsltu.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ugt_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsltu.vv v0, v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ugt <vscale x 8 x i64> %splat, %va
@@ -2428,18 +2470,25 @@ define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_uge_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_uge_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsleu.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_uge_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsleu.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat
@@ -2447,18 +2496,25 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_uge_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_uge_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsleu.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_uge_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsleu.vv v0, v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %splat, %va
@@ -2561,18 +2617,24 @@ define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ult_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ult_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsltu.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ult_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsltu.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat
@@ -2580,18 +2642,25 @@ define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ult_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ult_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsltu.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ult_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsltu.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %splat, %va
@@ -2682,18 +2751,24 @@ define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ule_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ule_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsleu.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ule_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsleu.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ule <vscale x 8 x i64> %va, %splat
@@ -2701,18 +2776,25 @@ define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_ule_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_ule_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsleu.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_ule_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsleu.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ule <vscale x 8 x i64> %splat, %va
@@ -2742,18 +2824,24 @@ define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sgt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sgt_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmslt.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sgt_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsgt.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sgt <vscale x 8 x i64> %va, %splat
@@ -2761,18 +2849,25 @@ define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sgt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sgt_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmslt.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sgt_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmslt.vv v0, v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sgt <vscale x 8 x i64> %splat, %va
@@ -2802,18 +2897,25 @@ define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sge_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sge_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsle.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sge_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsle.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat
@@ -2821,18 +2923,25 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sge_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sge_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsle.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sge_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsle.vv v0, v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %splat, %va
@@ -2911,18 +3020,24 @@ define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_slt_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_slt_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmslt.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_slt_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmslt.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat
@@ -2930,18 +3045,25 @@ define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_slt_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_slt_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmslt.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_slt_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmslt.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %splat, %va
@@ -3020,18 +3142,24 @@ define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x
}
define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sle_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sle_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsle.vv v0, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sle_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmsle.vx v0, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sle <vscale x 8 x i64> %va, %splat
@@ -3039,18 +3167,25 @@ define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
}
define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; CHECK-LABEL: icmp_sle_xv_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32-LABEL: icmp_sle_xv_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmsle.vv v0, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: icmp_sle_xv_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsle.vv v0, v16, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sle <vscale x 8 x i64> %splat, %va
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