[PATCH] D123231: [StructurizeCFG] Improve basic block ordering
Brendon Cahoon via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 09:08:01 PDT 2022
bcahoon created this revision.
bcahoon added a reviewer: sameerds.
Herald added subscribers: kerbowa, hiraditya, jvesely, MatzeB.
Herald added a project: All.
bcahoon requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
StructurizeCFG linearizes the successors of branching basic block
by adding Flow blocks to record the true/false path for branches
and back edges. This patch reduces the of Phi values needed to
capture the control flow path by improving the basic block
ordering.
Previously, StructurizeCFG adds loop exit blocks outside of the
loop. StructurizeCFG sets a boolean value to indicate the path
taken, and all exit block live values extend to after the loop.
For loops with a large number of exits blocks, this creates a
huge number of values that are maintained, which increases
compilation time and register pressure. This is problem
especially with ASAN, which adds early exits to unreachable
blocks for each instrumented check in the loop.
In specific cases, this patch reduces the number of values needed
after loop by moving the exit block to the loop. This is done
for blocks that have a single predecessor and single successor by
moving the block to appear just after the predecessor.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D123231
Files:
llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll
llvm/test/Transforms/StructurizeCFG/improve-order.ll
llvm/test/Transforms/StructurizeCFG/interleaved-loop-order.ll
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