[llvm] 9be6e7b - [X86] `lowerBuildVectorAsBroadcast()`: with AVX512VL, allow i64->XMM broadcasts from constant pool
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 08:33:57 PDT 2022
Author: Roman Lebedev
Date: 2022-04-06T18:33:40+03:00
New Revision: 9be6e7b0f2496efa76229f70654ebe6494dc2cf9
URL: https://github.com/llvm/llvm-project/commit/9be6e7b0f2496efa76229f70654ebe6494dc2cf9
DIFF: https://github.com/llvm/llvm-project/commit/9be6e7b0f2496efa76229f70654ebe6494dc2cf9.diff
LOG: [X86] `lowerBuildVectorAsBroadcast()`: with AVX512VL, allow i64->XMM broadcasts from constant pool
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D123221
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
llvm/test/CodeGen/X86/avx512-arith.ll
llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
llvm/test/CodeGen/X86/avx512-ext.ll
llvm/test/CodeGen/X86/avx512fp16-arith.ll
llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
llvm/test/CodeGen/X86/avx512vl-logic.ll
llvm/test/CodeGen/X86/fma-fneg-combine.ll
llvm/test/CodeGen/X86/fma_patterns.ll
llvm/test/CodeGen/X86/fp-round.ll
llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
llvm/test/CodeGen/X86/gfni-rotates.ll
llvm/test/CodeGen/X86/i64-to-float.ll
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
llvm/test/CodeGen/X86/movmsk-cmp.ll
llvm/test/CodeGen/X86/sadd_sat_vec.ll
llvm/test/CodeGen/X86/sat-add.ll
llvm/test/CodeGen/X86/ssub_sat_vec.ll
llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
llvm/test/CodeGen/X86/vec-copysign-avx512.ll
llvm/test/CodeGen/X86/vec_fabs.ll
llvm/test/CodeGen/X86/vec_int_to_fp.ll
llvm/test/CodeGen/X86/vector-fshl-128.ll
llvm/test/CodeGen/X86/vector-fshl-256.ll
llvm/test/CodeGen/X86/vector-fshl-512.ll
llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
llvm/test/CodeGen/X86/vector-fshr-128.ll
llvm/test/CodeGen/X86/vector-fshr-256.ll
llvm/test/CodeGen/X86/vector-fshr-512.ll
llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
llvm/test/CodeGen/X86/vector-popcnt-128.ll
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
llvm/test/CodeGen/X86/vector-rotate-128.ll
llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
llvm/test/CodeGen/X86/vector-shift-shl-128.ll
llvm/test/CodeGen/X86/vector-shift-shl-256.ll
llvm/test/CodeGen/X86/vector-tzcnt-128.ll
llvm/test/CodeGen/X86/vselect-pcmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 362d528914e86..a14be30293a86 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9503,7 +9503,8 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
// For size optimization, also splat v2f64 and v2i64, and for size opt
// with AVX2, also splat i8 and i16.
// With pattern matching, the VBROADCAST node may become a VMOVDDUP.
- if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
+ if (ScalarSize == 32 ||
+ (ScalarSize == 64 && (IsGE256 || Subtarget.hasVLX())) ||
(ScalarSize == 16 && Subtarget.hasFP16() && CVT.isFloatingPoint()) ||
(OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) {
const Constant *C = nullptr;
diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
index ca67da6de8c27..3e88b6f887ed9 100644
--- a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -1516,9 +1516,9 @@ define <2 x i64> @test_x86_avx2_psrlv_q_const() {
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
-; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
+; X64-AVX512VL-NEXT: # encoding: [0xc4,0xe2,0x79,0x59,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/avx512-arith.ll b/llvm/test/CodeGen/X86/avx512-arith.ll
index 70ab2b92531fe..6b39b67812cda 100644
--- a/llvm/test/CodeGen/X86/avx512-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512-arith.ll
@@ -303,7 +303,7 @@ define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
;
; AVX512VL-LABEL: imulq128_bcast:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@@ -332,7 +332,7 @@ define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
;
; SKX-LABEL: imulq128_bcast:
; SKX: # %bb.0:
-; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; SKX-NEXT: retq
%z = mul <2 x i64> %x, <i64 8086, i64 8086>
ret <2 x i64>%z
diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
index c8764f7254735..d89ebe0d896b0 100644
--- a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
+++ b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
@@ -177,7 +177,7 @@ define void @bcast_unfold_add_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_add_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB5_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -584,7 +584,8 @@ define void @bcast_unfold_or_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_or_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [3,3]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [3,3]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB17_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -786,7 +787,8 @@ define void @bcast_unfold_fneg_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fneg_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [-0.0E+0,-0.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [-0.0E+0,-0.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB23_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1003,7 +1005,8 @@ define void @bcast_unfold_fabs_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fabs_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [NaN,NaN]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB29_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1208,7 +1211,8 @@ define void @bcast_unfold_fadd_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fadd_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB35_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1410,7 +1414,8 @@ define void @bcast_unfold_fmul_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fmul_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [3.0E+0,3.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [3.0E+0,3.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB41_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1617,7 +1622,8 @@ define void @bcast_unfold_fdiv_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fdiv_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB47_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1865,7 +1871,8 @@ define void @bcast_unfold_fma213_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fma213_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB54_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1900,7 +1907,8 @@ define void @bcast_unfold_fma231_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fma231_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB55_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2186,7 +2194,8 @@ define void @bcast_unfold_fmax_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fmax_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB63_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2400,7 +2409,8 @@ define void @bcast_unfold_fmin_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fmin_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB69_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2611,7 +2621,7 @@ define void @bcast_unfold_smin_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_smin_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB75_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2819,7 +2829,7 @@ define void @bcast_unfold_smax_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_smax_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB81_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3027,7 +3037,7 @@ define void @bcast_unfold_umin_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_umin_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB87_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3235,7 +3245,7 @@ define void @bcast_unfold_umax_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_umax_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB93_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3449,13 +3459,13 @@ define void @bcast_unfold_pcmpgt_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpgt_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB99_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu 8192(%rdi,%rax), %xmm1
; CHECK-NEXT: vpcmpgtq %xmm0, %xmm1, %k1
-; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
+; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, 8192(%rdi,%rax)
; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: jne .LBB99_1
@@ -3668,13 +3678,13 @@ define void @bcast_unfold_pcmpeq_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpeq_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB105_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu 8192(%rdi,%rax), %xmm1
; CHECK-NEXT: vpcmpeqq %xmm0, %xmm1, %k1
-; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
+; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, 8192(%rdi,%rax)
; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: jne .LBB105_1
@@ -3890,13 +3900,13 @@ define void @bcast_unfold_pcmp_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmp_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB111_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltq %xmm0, %xmm1, %k1
-; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
+; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF
@@ -4115,13 +4125,13 @@ define void @bcast_unfold_pcmpu_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpu_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
+; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB117_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltuq %xmm0, %xmm1, %k1
-; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
+; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF
@@ -4340,8 +4350,10 @@ define void @bcast_unfold_cmp_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_cmp_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
-; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
-; CHECK-NEXT: vmovapd {{.*#+}} xmm1 = [3.0E+0,3.0E+0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
+; CHECK-NEXT: # xmm0 = mem[0,0]
+; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = [3.0E+0,3.0E+0]
+; CHECK-NEXT: # xmm1 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB123_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/X86/avx512-ext.ll b/llvm/test/CodeGen/X86/avx512-ext.ll
index aed158f98d95a..4032039c8ac89 100644
--- a/llvm/test/CodeGen/X86/avx512-ext.ll
+++ b/llvm/test/CodeGen/X86/avx512-ext.ll
@@ -3059,7 +3059,7 @@ define <2 x i64> @zext_2xi1_to_2xi64(<2 x i8> %x, <2 x i8> %y) #0 {
; AVX512DQNOBW: # %bb.0:
; AVX512DQNOBW-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
-; AVX512DQNOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512DQNOBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <2 x i8> %x, %y
%1 = zext <2 x i1> %mask to <2 x i64>
diff --git a/llvm/test/CodeGen/X86/avx512fp16-arith.ll b/llvm/test/CodeGen/X86/avx512fp16-arith.ll
index 5890d2c1db260..94bc94b2c2b55 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-arith.ll
@@ -370,7 +370,7 @@ declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
define <8 x half> @fcopysignv8f16(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fcopysignv8f16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; CHECK-NEXT: retq
%a = call <8 x half> @llvm.copysign.v8f16(<8 x half> %x, <8 x half> %y)
ret <8 x half> %a
diff --git a/llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
index 5307fecbf684a..cdf13b08d6871 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
@@ -761,7 +761,7 @@ define <4 x half> @test_s17tofp4(<4 x i17> %arg0) {
define <2 x half> @test_u33tofp2(<2 x i33> %arg0) {
; CHECK-LABEL: test_u33tofp2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vcvtuqq2ph %xmm0, %xmm0
; CHECK-NEXT: retq
%res = uitofp <2 x i33> %arg0 to <2 x half>
diff --git a/llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll b/llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
index d2ff3a1215dd7..e2ea8974f6551 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
@@ -357,7 +357,7 @@ define <8 x half> @fsub_bitcast_fneg_vec_undef_elts(<8 x half> %x, <8 x half> %y
define <8 x half> @fadd_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fadd_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
-; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; CHECK-NEXT: vaddph %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <8 x half> %y to <2 x i64>
@@ -370,7 +370,7 @@ define <8 x half> @fadd_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
define <8 x half> @fsub_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fsub_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
-; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; CHECK-NEXT: vsubph %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <8 x half> %y to <2 x i64>
diff --git a/llvm/test/CodeGen/X86/avx512vl-logic.ll b/llvm/test/CodeGen/X86/avx512vl-logic.ll
index 0d32ddc147fc0..7da3cf984175b 100644
--- a/llvm/test/CodeGen/X86/avx512vl-logic.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-logic.ll
@@ -168,7 +168,7 @@ entry:
define <2 x i64> @vpandq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -181,7 +181,7 @@ entry:
define <2 x i64> @vpandnq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -195,7 +195,7 @@ entry:
define <2 x i64> @vporq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vporq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -208,7 +208,7 @@ entry:
define <2 x i64> @vpxorq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxorq128:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/fma-fneg-combine.ll b/llvm/test/CodeGen/X86/fma-fneg-combine.ll
index 47a70e5397156..fa96093a00f52 100644
--- a/llvm/test/CodeGen/X86/fma-fneg-combine.ll
+++ b/llvm/test/CodeGen/X86/fma-fneg-combine.ll
@@ -226,11 +226,17 @@ define <8 x double> @test9_nsz(<8 x double> %a, <8 x double> %b, <8 x double> %c
}
define <2 x double> @test10(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
-; CHECK-LABEL: test10:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
-; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT: retq
+; SKX-LABEL: test10:
+; SKX: # %bb.0: # %entry
+; SKX-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
+; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; SKX-NEXT: retq
+;
+; KNL-LABEL: test10:
+; KNL: # %bb.0: # %entry
+; KNL-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
+; KNL-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; KNL-NEXT: retq
entry:
%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 -1, i32 4) #2
%sub.i = fsub <2 x double> <double -0.0, double -0.0>, %0
@@ -305,7 +311,7 @@ entry:
define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
; SKX-LABEL: test13:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm3
; SKX-NEXT: vfnmadd213sd {{.*#+}} xmm1 = -(xmm0 * xmm1) + xmm2
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vmovsd %xmm1, %xmm3, %xmm3 {%k1}
diff --git a/llvm/test/CodeGen/X86/fma_patterns.ll b/llvm/test/CodeGen/X86/fma_patterns.ll
index ee1e7cb4ed162..99a7e9f1ee0a2 100644
--- a/llvm/test/CodeGen/X86/fma_patterns.ll
+++ b/llvm/test/CodeGen/X86/fma_patterns.ll
@@ -1481,7 +1481,8 @@ define <2 x double> @test_v2f64_interp(<2 x double> %x, <2 x double> %y, <2 x do
;
; AVX512-INFS-LABEL: test_v2f64_interp:
; AVX512-INFS: # %bb.0:
-; AVX512-INFS-NEXT: vmovapd {{.*#+}} xmm3 = [1.0E+0,1.0E+0]
+; AVX512-INFS-NEXT: vmovddup {{.*#+}} xmm3 = [1.0E+0,1.0E+0]
+; AVX512-INFS-NEXT: # xmm3 = mem[0,0]
; AVX512-INFS-NEXT: vsubpd %xmm2, %xmm3, %xmm3
; AVX512-INFS-NEXT: vmulpd %xmm3, %xmm1, %xmm1
; AVX512-INFS-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm2 * xmm0) + xmm1
diff --git a/llvm/test/CodeGen/X86/fp-round.ll b/llvm/test/CodeGen/X86/fp-round.ll
index 955501544ff55..7bcbdb2f40ea5 100644
--- a/llvm/test/CodeGen/X86/fp-round.ll
+++ b/llvm/test/CodeGen/X86/fp-round.ll
@@ -138,7 +138,7 @@ define double @round_f64(double %x) {
; AVX512-LABEL: round_f64:
; AVX512: ## %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
-; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
; AVX512-NEXT: retq
@@ -239,8 +239,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
;
; AVX512-LABEL: round_v2f64:
; AVX512: ## %bb.0:
-; AVX512-NEXT: vmovdqa {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
-; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
+; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
index fe275ba8605b3..1f5236311b463 100644
--- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
+++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
@@ -31,7 +31,7 @@ define <16 x i8> @splatconstant_fshl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind
; GFNIAVX512: # %bb.0:
; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm2
; GFNIAVX512-NEXT: vpsrlw $5, %xmm1, %xmm0
-; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %res
diff --git a/llvm/test/CodeGen/X86/gfni-rotates.ll b/llvm/test/CodeGen/X86/gfni-rotates.ll
index 0f7c4e43ef97c..44581cb97e033 100644
--- a/llvm/test/CodeGen/X86/gfni-rotates.ll
+++ b/llvm/test/CodeGen/X86/gfni-rotates.ll
@@ -32,7 +32,7 @@ define <16 x i8> @splatconstant_rotl_v16i8(<16 x i8> %a) nounwind {
; GFNIAVX512: # %bb.0:
; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm1
; GFNIAVX512-NEXT: vpsrlw $5, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %res
diff --git a/llvm/test/CodeGen/X86/i64-to-float.ll b/llvm/test/CodeGen/X86/i64-to-float.ll
index bedc27e6d6491..b4cc49f9713aa 100644
--- a/llvm/test/CodeGen/X86/i64-to-float.ll
+++ b/llvm/test/CodeGen/X86/i64-to-float.ll
@@ -366,16 +366,16 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X64-AVX512F-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; X64-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-AVX512F-NEXT: retq
;
; X64-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512DQ: # %bb.0:
-; X64-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; X64-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%clo = icmp slt <2 x i64> %a, <i64 -255, i64 -255>
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
index 035a1fbd0d10f..c73ebe96685bf 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
@@ -2499,8 +2499,8 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@@ -2681,8 +2681,8 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -2850,8 +2850,8 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
index f36097a2cd464..25047c8de8c0d 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
@@ -2178,7 +2178,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@@ -2340,7 +2340,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@@ -2489,7 +2489,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
-; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/movmsk-cmp.ll b/llvm/test/CodeGen/X86/movmsk-cmp.ll
index 70a086e96e6e4..779f9dcdfd9ab 100644
--- a/llvm/test/CodeGen/X86/movmsk-cmp.ll
+++ b/llvm/test/CodeGen/X86/movmsk-cmp.ll
@@ -2128,7 +2128,7 @@ define i1 @allones_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@@ -2170,7 +2170,7 @@ define i1 @allzeros_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and1:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@@ -3417,7 +3417,7 @@ define i1 @allones_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@@ -3459,7 +3459,7 @@ define i1 @allzeros_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and4:
; SKX: # %bb.0:
-; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sadd_sat_vec.ll b/llvm/test/CodeGen/X86/sadd_sat_vec.ll
index 025ddcd48cf34..d4550514fda83 100644
--- a/llvm/test/CodeGen/X86/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/sadd_sat_vec.ll
@@ -1232,8 +1232,8 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm0, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
-; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
+; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sat-add.ll b/llvm/test/CodeGen/X86/sat-add.ll
index 3feff29b1773e..9c8480f2e4340 100644
--- a/llvm/test/CodeGen/X86/sat-add.ll
+++ b/llvm/test/CodeGen/X86/sat-add.ll
@@ -667,8 +667,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_min:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
@@ -736,8 +736,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, %a
@@ -803,8 +803,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
diff --git a/llvm/test/CodeGen/X86/ssub_sat_vec.ll b/llvm/test/CodeGen/X86/ssub_sat_vec.ll
index 3f31c0bb2c248..c6d7150d1dd2f 100644
--- a/llvm/test/CodeGen/X86/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/ssub_sat_vec.ll
@@ -1329,8 +1329,8 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm0, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
-; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
-; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
+; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
index 280c97bcefedc..ac03433808488 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
@@ -257,11 +257,11 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t3_wide:
; CHECK-AVX512VL: # %bb.0:
-; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
+; CHECK-AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
-; CHECK-AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/vec-copysign-avx512.ll b/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
index f47187fd05267..7fb692411a0ea 100644
--- a/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
+++ b/llvm/test/CodeGen/X86/vec-copysign-avx512.ll
@@ -32,7 +32,7 @@ define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
; CHECK-LABEL: v2f64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; CHECK-NEXT: retq
%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
ret <2 x double> %tmp
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 64bd0f7939685..fb01a18ea9280 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -7,15 +7,35 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VLDQ
define <2 x double> @fabs_v2f64(<2 x double> %p) {
-; X86-LABEL: fabs_v2f64:
-; X86: # %bb.0:
-; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X86-NEXT: retl
+; X86-AVX-LABEL: fabs_v2f64:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: retl
;
-; X64-LABEL: fabs_v2f64:
-; X64: # %bb.0:
-; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-NEXT: retq
+; X86-AVX512VL-LABEL: fabs_v2f64:
+; X86-AVX512VL: # %bb.0:
+; X86-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
+; X86-AVX512VL-NEXT: retl
+;
+; X86-AVX512VLDQ-LABEL: fabs_v2f64:
+; X86-AVX512VLDQ: # %bb.0:
+; X86-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
+; X86-AVX512VLDQ-NEXT: retl
+;
+; X64-AVX-LABEL: fabs_v2f64:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: retq
+;
+; X64-AVX512VL-LABEL: fabs_v2f64:
+; X64-AVX512VL: # %bb.0:
+; X64-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; X64-AVX512VL-NEXT: retq
+;
+; X64-AVX512VLDQ-LABEL: fabs_v2f64:
+; X64-AVX512VLDQ: # %bb.0:
+; X64-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; X64-AVX512VLDQ-NEXT: retq
%t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
ret <2 x double> %t
}
diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
index e95afd00304f2..901c2a4aee7ec 100644
--- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll
+++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
@@ -626,10 +626,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@@ -3300,10 +3300,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@@ -5710,15 +5710,16 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VL-LABEL: PR43609:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
; AVX512VL-NEXT: vpor %xmm4, %xmm3, %xmm3
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; AVX512VL-NEXT: vpor %xmm5, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
+; AVX512VL-NEXT: vmovddup {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
+; AVX512VL-NEXT: # xmm6 = mem[0,0]
; AVX512VL-NEXT: vsubpd %xmm6, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
@@ -5727,7 +5728,8 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
; AVX512VL-NEXT: vpor %xmm5, %xmm1, %xmm1
; AVX512VL-NEXT: vsubpd %xmm6, %xmm1, %xmm1
; AVX512VL-NEXT: vaddpd %xmm1, %xmm2, %xmm1
-; AVX512VL-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
+; AVX512VL-NEXT: vmovddup {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
+; AVX512VL-NEXT: # xmm2 = mem[0,0]
; AVX512VL-NEXT: vaddpd %xmm2, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm2, %xmm1, %xmm1
; AVX512VL-NEXT: vmovupd %xmm0, (%rdi)
@@ -5750,10 +5752,11 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VLDQ-LABEL: PR43609:
; AVX512VLDQ: # %bb.0:
-; AVX512VLDQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512VLDQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm1, %xmm1
-; AVX512VLDQ-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
+; AVX512VLDQ-NEXT: vmovddup {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
+; AVX512VLDQ-NEXT: # xmm2 = mem[0,0]
; AVX512VLDQ-NEXT: vaddpd %xmm2, %xmm0, %xmm0
; AVX512VLDQ-NEXT: vaddpd %xmm2, %xmm1, %xmm1
; AVX512VLDQ-NEXT: vmovupd %xmm0, (%rdi)
diff --git a/llvm/test/CodeGen/X86/vector-fshl-128.ll b/llvm/test/CodeGen/X86/vector-fshl-128.ll
index 2d4710d55926c..1c2d4c1d80986 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-128.ll
@@ -106,7 +106,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VL-LABEL: var_funnnel_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
@@ -138,7 +138,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VLBW-LABEL: var_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
@@ -976,7 +976,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
@@ -1008,7 +1008,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
@@ -2365,7 +2365,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@@ -2390,14 +2390,14 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLBW-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshl-256.ll b/llvm/test/CodeGen/X86/vector-fshl-256.ll
index 9d14f227f3a89..0407f43d305fe 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-256.ll
@@ -783,7 +783,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
@@ -814,7 +814,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v4i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/vector-fshl-512.ll b/llvm/test/CodeGen/X86/vector-fshl-512.ll
index 4776f004bef4f..dc595801d74b5 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-512.ll
@@ -437,7 +437,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v8i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %zmm1, %zmm1
; AVX512VL-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
@@ -465,7 +465,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v8i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
diff --git a/llvm/test/CodeGen/X86/vector-fshl-rot-128.ll b/llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
index c2ef8ceaba811..df26de9d7b2a6 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
@@ -1834,7 +1834,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@@ -1850,7 +1850,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_funnnel_v16i8:
@@ -1866,7 +1866,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll
index aa490b4966b66..a549d3fd53431 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll
@@ -106,7 +106,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VL-LABEL: var_funnnel_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -138,7 +138,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VLBW-LABEL: var_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -1065,7 +1065,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -1097,7 +1097,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -2317,7 +2317,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@@ -2342,14 +2342,14 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLBW-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm1, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 32b2d9f835d82..3a78ca84e861b 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -814,7 +814,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -845,7 +845,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v4i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
diff --git a/llvm/test/CodeGen/X86/vector-fshr-512.ll b/llvm/test/CodeGen/X86/vector-fshr-512.ll
index 4501fc0c94931..e9dd400c1f78a 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-512.ll
@@ -435,7 +435,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v8i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@@ -464,7 +464,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v8i64:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
+; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
diff --git a/llvm/test/CodeGen/X86/vector-fshr-rot-128.ll b/llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
index 566695fd3656c..e1dcaa82b3278 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
@@ -1880,7 +1880,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@@ -1896,7 +1896,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_funnnel_v16i8:
@@ -1912,7 +1912,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
index f95178f1bfcdf..46792ee23181e 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
@@ -16989,7 +16989,7 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17094,7 +17094,7 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_2_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17276,7 +17276,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_2_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17296,7 +17296,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17463,7 +17463,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_3_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17484,7 +17484,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17648,7 +17648,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_3_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17668,7 +17668,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -17835,7 +17835,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_4_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -17856,7 +17856,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18020,7 +18020,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_4_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18040,7 +18040,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18207,7 +18207,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_5_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18228,7 +18228,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18392,7 +18392,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_5_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18412,7 +18412,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18579,7 +18579,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_6_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18600,7 +18600,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18764,7 +18764,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_6_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18784,7 +18784,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -18951,7 +18951,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_7_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -18972,7 +18972,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19136,7 +19136,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_7_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19156,7 +19156,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19323,7 +19323,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_8_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19344,7 +19344,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19508,7 +19508,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_8_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19528,7 +19528,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19695,7 +19695,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_9_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19716,7 +19716,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -19880,7 +19880,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_9_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -19900,7 +19900,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20067,7 +20067,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_10_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20088,7 +20088,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20252,7 +20252,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_10_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20272,7 +20272,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20439,7 +20439,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_11_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20460,7 +20460,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20624,7 +20624,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_11_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20644,7 +20644,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20811,7 +20811,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_12_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -20832,7 +20832,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -20996,7 +20996,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_12_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21016,7 +21016,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21183,7 +21183,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_13_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21204,7 +21204,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21368,7 +21368,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_13_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21388,7 +21388,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21555,7 +21555,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_14_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21576,7 +21576,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21740,7 +21740,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_14_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21760,7 +21760,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -21927,7 +21927,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_15_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -21948,7 +21948,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22112,7 +22112,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_15_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22132,7 +22132,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22299,7 +22299,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_16_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22320,7 +22320,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22484,7 +22484,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_16_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22504,7 +22504,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22671,7 +22671,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_17_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22692,7 +22692,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -22856,7 +22856,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_17_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -22876,7 +22876,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23043,7 +23043,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_18_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23064,7 +23064,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23228,7 +23228,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_18_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23248,7 +23248,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23415,7 +23415,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_19_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23436,7 +23436,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23600,7 +23600,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_19_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23620,7 +23620,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23787,7 +23787,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_20_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23808,7 +23808,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -23972,7 +23972,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_20_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -23992,7 +23992,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24159,7 +24159,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_21_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24180,7 +24180,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24344,7 +24344,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_21_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24364,7 +24364,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24531,7 +24531,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_22_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24552,7 +24552,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24716,7 +24716,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_22_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24736,7 +24736,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -24903,7 +24903,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_23_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -24924,7 +24924,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25088,7 +25088,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_23_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25108,7 +25108,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25275,7 +25275,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_24_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25296,7 +25296,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25460,7 +25460,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_24_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25480,7 +25480,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25647,7 +25647,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_25_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25668,7 +25668,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -25832,7 +25832,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_25_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -25852,7 +25852,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26019,7 +26019,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_26_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26040,7 +26040,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26204,7 +26204,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_26_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26224,7 +26224,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26391,7 +26391,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_27_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26412,7 +26412,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26576,7 +26576,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_27_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26596,7 +26596,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26763,7 +26763,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_28_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26784,7 +26784,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -26948,7 +26948,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_28_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -26968,7 +26968,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27135,7 +27135,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_29_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27156,7 +27156,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27320,7 +27320,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_29_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27340,7 +27340,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27507,7 +27507,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_30_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27528,7 +27528,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27692,7 +27692,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_30_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27712,7 +27712,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -27879,7 +27879,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_31_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -27900,7 +27900,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28064,7 +28064,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_31_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28084,7 +28084,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28251,7 +28251,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_32_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28272,7 +28272,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28436,7 +28436,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_32_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28456,7 +28456,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28623,7 +28623,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_33_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28644,7 +28644,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28808,7 +28808,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_33_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -28828,7 +28828,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -28995,7 +28995,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_34_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29016,7 +29016,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29180,7 +29180,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_34_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29200,7 +29200,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29367,7 +29367,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_35_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29388,7 +29388,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29552,7 +29552,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_35_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29572,7 +29572,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29739,7 +29739,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_36_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29760,7 +29760,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -29924,7 +29924,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_36_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -29944,7 +29944,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30111,7 +30111,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_37_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30132,7 +30132,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30296,7 +30296,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_37_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30316,7 +30316,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30483,7 +30483,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_38_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30504,7 +30504,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30668,7 +30668,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_38_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30688,7 +30688,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -30855,7 +30855,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_39_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -30876,7 +30876,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31040,7 +31040,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_39_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31060,7 +31060,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31227,7 +31227,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_40_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31248,7 +31248,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31412,7 +31412,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_40_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31432,7 +31432,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31599,7 +31599,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_41_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31620,7 +31620,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31784,7 +31784,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_41_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31804,7 +31804,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -31971,7 +31971,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_42_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -31992,7 +31992,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32156,7 +32156,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_42_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32176,7 +32176,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32343,7 +32343,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_43_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32364,7 +32364,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32528,7 +32528,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_43_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32548,7 +32548,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32715,7 +32715,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_44_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32736,7 +32736,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -32900,7 +32900,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_44_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -32920,7 +32920,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33087,7 +33087,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_45_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33108,7 +33108,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33272,7 +33272,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_45_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33292,7 +33292,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33459,7 +33459,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_46_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33480,7 +33480,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33644,7 +33644,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_46_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33664,7 +33664,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -33831,7 +33831,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_47_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -33852,7 +33852,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34016,7 +34016,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_47_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34036,7 +34036,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34203,7 +34203,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_48_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34224,7 +34224,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34388,7 +34388,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_48_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34408,7 +34408,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34575,7 +34575,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_49_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34596,7 +34596,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34760,7 +34760,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_49_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34780,7 +34780,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -34947,7 +34947,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_50_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -34968,7 +34968,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35132,7 +35132,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_50_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35152,7 +35152,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35319,7 +35319,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_51_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35340,7 +35340,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35504,7 +35504,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_51_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35524,7 +35524,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35691,7 +35691,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_52_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35712,7 +35712,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -35876,7 +35876,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_52_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -35896,7 +35896,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36063,7 +36063,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_53_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36084,7 +36084,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36248,7 +36248,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_53_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36268,7 +36268,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36435,7 +36435,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_54_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36456,7 +36456,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36620,7 +36620,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_54_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36640,7 +36640,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36807,7 +36807,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_55_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -36828,7 +36828,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -36992,7 +36992,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_55_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37012,7 +37012,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37179,7 +37179,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_56_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37200,7 +37200,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37364,7 +37364,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_56_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37384,7 +37384,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37551,7 +37551,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_57_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37572,7 +37572,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37736,7 +37736,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_57_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37756,7 +37756,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -37923,7 +37923,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_58_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -37944,7 +37944,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38108,7 +38108,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_58_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38128,7 +38128,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38295,7 +38295,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_59_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38316,7 +38316,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38480,7 +38480,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_59_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38500,7 +38500,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38667,7 +38667,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_60_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38688,7 +38688,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -38852,7 +38852,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_60_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -38872,7 +38872,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39039,7 +39039,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_61_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39060,7 +39060,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39224,7 +39224,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_61_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39244,7 +39244,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39411,7 +39411,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_62_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39432,7 +39432,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39596,7 +39596,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ugt_62_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39616,7 +39616,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpnleuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
@@ -39783,7 +39783,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ult_63_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VPOPCNTDQVL-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VPOPCNTDQVL-NEXT: retq
@@ -39804,7 +39804,7 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; BITALG-NEXT: vpopcntb %xmm0, %xmm0
; BITALG-NEXT: vpxor %xmm1, %xmm1, %xmm1
; BITALG-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; BITALG-NEXT: vpcmpltuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; BITALG-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; BITALG-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; BITALG-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128.ll b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
index b25c3ae1271b2..a03e34dc46b32 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
@@ -753,7 +753,8 @@ define <2 x i64> @eq_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: eq_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [1,1]
+; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: eq_1_v2i64:
@@ -888,7 +889,8 @@ define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ne_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
-; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [1,1]
+; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index 59c7db337fd2a..11e3a892d4d0f 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -836,11 +836,30 @@ define i1 @trunc_v2i64(<2 x i64> %a0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
-; AVX-LABEL: trunc_v2i64:
-; AVX: # %bb.0:
-; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; AVX-NEXT: sete %al
-; AVX-NEXT: retq
+; AVX1-LABEL: trunc_v2i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX1-NEXT: sete %al
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: trunc_v2i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: retq
+;
+; AVX512BW-LABEL: trunc_v2i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX512BW-NEXT: sete %al
+; AVX512BW-NEXT: retq
+;
+; AVX512BWVL-LABEL: trunc_v2i64:
+; AVX512BWVL: # %bb.0:
+; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [65535,65535]
+; AVX512BWVL-NEXT: vptest %xmm1, %xmm0
+; AVX512BWVL-NEXT: sete %al
+; AVX512BWVL-NEXT: retq
%1 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a0)
%2 = trunc i64 %1 to i16
%3 = icmp eq i16 %2, 0
@@ -1028,12 +1047,34 @@ define zeroext i1 @PR44781(%struct.Box* %0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
-; AVX-LABEL: PR44781:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovdqu (%rdi), %xmm0
-; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; AVX-NEXT: sete %al
-; AVX-NEXT: retq
+; AVX1-LABEL: PR44781:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX1-NEXT: sete %al
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: PR44781:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: retq
+;
+; AVX512BW-LABEL: PR44781:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vmovdqu (%rdi), %xmm0
+; AVX512BW-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX512BW-NEXT: sete %al
+; AVX512BW-NEXT: retq
+;
+; AVX512BWVL-LABEL: PR44781:
+; AVX512BWVL: # %bb.0:
+; AVX512BWVL-NEXT: vmovdqu (%rdi), %xmm0
+; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64424509455,64424509455]
+; AVX512BWVL-NEXT: vptest %xmm1, %xmm0
+; AVX512BWVL-NEXT: sete %al
+; AVX512BWVL-NEXT: retq
%2 = bitcast %struct.Box* %0 to <4 x i32>*
%3 = load <4 x i32>, <4 x i32>* %2, align 4
%4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %3)
diff --git a/llvm/test/CodeGen/X86/vector-rotate-128.ll b/llvm/test/CodeGen/X86/vector-rotate-128.ll
index f537a9c5429e3..637e08e790b50 100644
--- a/llvm/test/CodeGen/X86/vector-rotate-128.ll
+++ b/llvm/test/CodeGen/X86/vector-rotate-128.ll
@@ -1783,7 +1783,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_v16i8:
@@ -1799,7 +1799,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_v16i8:
@@ -1815,7 +1815,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_rotate_v16i8:
@@ -2081,7 +2081,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
@@ -2098,7 +2098,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLBW-NEXT: retq
;
@@ -2115,7 +2115,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
+; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll b/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
index 821a9803bed78..b6f374e2ca68c 100644
--- a/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
@@ -972,7 +972,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsraq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-ashr-256.ll b/llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
index e9a970157b053..c1997bfdcf32d 100644
--- a/llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
@@ -1062,7 +1062,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsraq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll b/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
index 6b5a76f2a0e47..b89c767766928 100644
--- a/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
@@ -795,7 +795,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-lshr-256.ll b/llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
index a36d484319312..d0d53f827e8b7 100644
--- a/llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
@@ -859,7 +859,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll
index 73e2b29fb3d82..b6d45355341e7 100644
--- a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll
@@ -702,7 +702,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsllq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
index cfb4fef06fd81..661595d9a4f4f 100644
--- a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
@@ -784,7 +784,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
index 93a88c1488d11..caeb0015d4b52 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
@@ -140,7 +140,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; AVX512CDVL-NEXT: vpaddq %xmm1, %xmm0, %xmm1
; AVX512CDVL-NEXT: vpandn %xmm1, %xmm0, %xmm0
; AVX512CDVL-NEXT: vplzcntq %xmm0, %xmm0
-; AVX512CDVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64]
+; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpsubq %xmm0, %xmm1, %xmm0
; AVX512CDVL-NEXT: retq
;
@@ -341,7 +341,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; AVX512CDVL-NEXT: vpaddq %xmm1, %xmm0, %xmm1
; AVX512CDVL-NEXT: vpandn %xmm1, %xmm0, %xmm0
; AVX512CDVL-NEXT: vplzcntq %xmm0, %xmm0
-; AVX512CDVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64]
+; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpsubq %xmm0, %xmm1, %xmm0
; AVX512CDVL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vselect-pcmp.ll b/llvm/test/CodeGen/X86/vselect-pcmp.ll
index 75434e45558c5..701522f9ce522 100644
--- a/llvm/test/CodeGen/X86/vselect-pcmp.ll
+++ b/llvm/test/CodeGen/X86/vselect-pcmp.ll
@@ -653,7 +653,7 @@ define <2 x i64> @blend_splatmax_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2
;
; AVX512VL-LABEL: blend_splatmax_mask_cond_v2i64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
+; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;
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