[PATCH] D123221: [X86] `lowerBuildVectorAsBroadcast()`: with AVX512VL, allow i64 broadcasts from constant pool

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 420872.
lebedev.ri marked an inline comment as done.
lebedev.ri retitled this revision from "[X86] `lowerBuildVectorAsBroadcast()`: with AVX512, allow i64 broadcasts from constant pool" to "[X86] `lowerBuildVectorAsBroadcast()`: with AVX512VL, allow i64 broadcasts from constant pool".
lebedev.ri added a comment.

Require AVX512VL, not just plain AVX512F.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123221/new/

https://reviews.llvm.org/D123221

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
  llvm/test/CodeGen/X86/avx512-arith.ll
  llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
  llvm/test/CodeGen/X86/avx512-ext.ll
  llvm/test/CodeGen/X86/avx512fp16-arith.ll
  llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
  llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
  llvm/test/CodeGen/X86/avx512vl-logic.ll
  llvm/test/CodeGen/X86/fma-fneg-combine.ll
  llvm/test/CodeGen/X86/fma_patterns.ll
  llvm/test/CodeGen/X86/fp-round.ll
  llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
  llvm/test/CodeGen/X86/gfni-rotates.ll
  llvm/test/CodeGen/X86/i64-to-float.ll
  llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
  llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
  llvm/test/CodeGen/X86/vec-copysign-avx512.ll
  llvm/test/CodeGen/X86/vec_fabs.ll
  llvm/test/CodeGen/X86/vec_int_to_fp.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
  llvm/test/CodeGen/X86/vector-popcnt-128.ll
  llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
  llvm/test/CodeGen/X86/vector-shift-shl-128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-256.ll
  llvm/test/CodeGen/X86/vector-tzcnt-128.ll
  llvm/test/CodeGen/X86/vselect-pcmp.ll

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