[llvm] f743159 - [AMDGPU] Regenerate pv-packing.ll test

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 6 04:33:29 PDT 2022


Author: Simon Pilgrim
Date: 2022-04-06T12:23:17+01:00
New Revision: f743159037b934c771d6e57181aff7559ee6811d

URL: https://github.com/llvm/llvm-project/commit/f743159037b934c771d6e57181aff7559ee6811d
DIFF: https://github.com/llvm/llvm-project/commit/f743159037b934c771d6e57181aff7559ee6811d.diff

LOG: [AMDGPU] Regenerate pv-packing.ll test

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/pv-packing.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/pv-packing.ll b/llvm/test/CodeGen/AMDGPU/pv-packing.ll
index b01c00daede34..fbd6fc593d959 100644
--- a/llvm/test/CodeGen/AMDGPU/pv-packing.ll
+++ b/llvm/test/CodeGen/AMDGPU/pv-packing.ll
@@ -1,9 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
 
-;CHECK: DOT4  T{{[0-9]\.X}}
-;CHECK: MULADD_IEEE * T{{[0-9]\.W}}
-
 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
+; CHECK-LABEL: main:
+; CHECK:       ; %bb.0: ; %main_body
+; CHECK-NEXT:    CALL_FS
+; CHECK-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
+; CHECK-NEXT:    EXPORT T0.X___
+; CHECK-NEXT:    CF_END
+; CHECK-NEXT:    ALU clause starting at 4:
+; CHECK-NEXT:     DOT4 T0.X, KC0[0].X, KC0[0].X,
+; CHECK-NEXT:     DOT4 T0.Y (MASKED), KC0[0].Y, KC0[0].Y,
+; CHECK-NEXT:     DOT4 T0.Z (MASKED), KC0[0].Z, KC0[0].Z,
+; CHECK-NEXT:     DOT4 * T0.W (MASKED), KC0[0].W, KC0[0].W,
+; CHECK-NEXT:     MULADD_IEEE T2.X, T1.X, T2.X, T3.X,
+; CHECK-NEXT:     MULADD_IEEE T0.Y, T1.Y, T2.Y, T3.Y,
+; CHECK-NEXT:     MULADD_IEEE T0.Z, T1.Z, T2.Z, T3.Z,
+; CHECK-NEXT:     MULADD_IEEE * T0.W, PV.X, PV.X, T1.X, BS:VEC_120/SCL_212
+; CHECK-NEXT:     DOT4 T0.X, T2.X, KC0[1].X,
+; CHECK-NEXT:     DOT4 T0.Y (MASKED), T0.Y, KC0[1].Y,
+; CHECK-NEXT:     DOT4 T0.Z (MASKED), T0.Z, KC0[1].Z,
+; CHECK-NEXT:     DOT4 * T0.W (MASKED), T0.W, KC0[1].W,
 main_body:
   %0 = extractelement <4 x float> %reg1, i32 0
   %1 = extractelement <4 x float> %reg1, i32 1


        


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