[llvm] 83a798d - [CodeGen] Place SDNode debug ID declaration under appropriate #if
Daniil Kovalev via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 04:17:20 PDT 2022
Author: Daniil Kovalev
Date: 2022-04-06T14:09:32+03:00
New Revision: 83a798d4b0e17ac41d5430f1290d3661343eee1e
URL: https://github.com/llvm/llvm-project/commit/83a798d4b0e17ac41d5430f1290d3661343eee1e
DIFF: https://github.com/llvm/llvm-project/commit/83a798d4b0e17ac41d5430f1290d3661343eee1e.diff
LOG: [CodeGen] Place SDNode debug ID declaration under appropriate #if
Place PersistentId declaration under #if LLVM_ENABLE_ABI_BREAKING_CHECKS to
reduce memory usage when it is not needed.
Differential Revision: https://reviews.llvm.org/D120714
Added:
Modified:
llvm/cmake/modules/HandleLLVMOptions.cmake
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/test/CodeGen/AArch64/pow.75.ll
llvm/test/CodeGen/AArch64/split-vector-insert.ll
llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
llvm/test/CodeGen/ARM/pow.75.ll
llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
llvm/test/CodeGen/Mips/address-selection.ll
llvm/test/CodeGen/Mips/cconv/byval.ll
llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
llvm/test/CodeGen/Mips/frameindex.ll
llvm/test/CodeGen/Mips/llvm-ir/isel.ll
llvm/test/CodeGen/PowerPC/add_cmp.ll
llvm/test/CodeGen/PowerPC/fmf-propagation.ll
llvm/test/CodeGen/PowerPC/pow.75.ll
llvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll
llvm/test/CodeGen/SystemZ/isel-debug.ll
llvm/test/CodeGen/VE/Vector/vp_srem.ll
llvm/test/CodeGen/VE/Vector/vp_urem.ll
llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll
llvm/test/CodeGen/X86/fmf-propagation.ll
llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
llvm/test/CodeGen/X86/pow.75.ll
llvm/test/lit.cfg.py
llvm/test/lit.site.cfg.py.in
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu-isel-support.test
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai-isel-support.test
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-isel-support.test
Removed:
################################################################################
diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake
index ef05cc48ce5fe..d390212cf242a 100644
--- a/llvm/cmake/modules/HandleLLVMOptions.cmake
+++ b/llvm/cmake/modules/HandleLLVMOptions.cmake
@@ -113,14 +113,17 @@ string(TOUPPER "${LLVM_ABI_BREAKING_CHECKS}" uppercase_LLVM_ABI_BREAKING_CHECKS)
if( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "WITH_ASSERTS" )
if( LLVM_ENABLE_ASSERTIONS )
set( LLVM_ENABLE_ABI_BREAKING_CHECKS 1 )
+ else()
+ set( LLVM_ENABLE_ABI_BREAKING_CHECKS 0 )
endif()
elseif( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "FORCE_ON" )
set( LLVM_ENABLE_ABI_BREAKING_CHECKS 1 )
elseif( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "FORCE_OFF" )
- # We don't need to do anything special to turn off ABI breaking checks.
+ set( LLVM_ENABLE_ABI_BREAKING_CHECKS 0 )
elseif( NOT DEFINED LLVM_ABI_BREAKING_CHECKS )
# Treat LLVM_ABI_BREAKING_CHECKS like "FORCE_OFF" when it has not been
# defined.
+ set( LLVM_ENABLE_ABI_BREAKING_CHECKS 0 )
else()
message(FATAL_ERROR "Unknown value for LLVM_ABI_BREAKING_CHECKS: \"${LLVM_ABI_BREAKING_CHECKS}\"!")
endif()
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 651b404a35687..543a5bb45139c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -280,7 +280,9 @@ class SelectionDAG {
DenseMap<const SDNode *, CallSiteDbgInfo> SDCallSiteDbgInfo;
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
uint16_t NextPersistentId = 0;
+#endif
/// Are instruction referencing variable locations desired for this function?
bool UseInstrRefDebugInfo = false;
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 6b2491358a3f0..4eea19a2f89ee 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -617,7 +617,9 @@ END_TWO_BYTE_PACK()
public:
/// Unique and persistent id per SDNode in the DAG.
/// Used for debug printing.
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
uint16_t PersistentId;
+#endif
//===--------------------------------------------------------------------===//
// Accessors
@@ -1220,7 +1222,9 @@ class HandleSDNode : public SDNode {
: SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
// HandleSDNodes are never inserted into the DAG, so they won't be
// auto-numbered. Use ID 65535 as a sentinel.
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
PersistentId = 0xffff;
+#endif
// Manually set up the operand list. This node type is special in that it's
// always stack allocated and SelectionDAG does not manage its operands.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c1eedd35d7743..f73bf015b276c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1066,8 +1066,10 @@ static void VerifySDNode(SDNode *N) {
/// verification and other common operations when a new node is allocated.
void SelectionDAG::InsertNode(SDNode *N) {
AllNodes.push_back(N);
-#ifndef NDEBUG
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
N->PersistentId = NextPersistentId++;
+#endif
+#ifndef NDEBUG
VerifySDNode(N);
#endif
for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
@@ -1271,7 +1273,7 @@ void SelectionDAG::allnodes_clear() {
AllNodes.remove(AllNodes.begin());
while (!AllNodes.empty())
DeallocateNode(&AllNodes.front());
-#ifndef NDEBUG
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
NextPersistentId = 0;
#endif
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 874073bc456a1..ec0503291bfc1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -504,10 +504,10 @@ const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
static Printable PrintNodeId(const SDNode &Node) {
return Printable([&Node](raw_ostream &OS) {
-#ifndef NDEBUG
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
OS << 't' << Node.PersistentId;
#else
- OS << (const void*)&Node;
+ OS << (const void *)&Node;
#endif
});
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index b66eeb6d2bb1a..4c43eaf1b39fa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -77,7 +77,7 @@ namespace llvm {
const SelectionDAG *Graph) {
std::string R;
raw_string_ostream OS(R);
-#ifndef NDEBUG
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
OS << 't' << Node->PersistentId;
#else
OS << static_cast<const void *>(Node);
diff --git a/llvm/test/CodeGen/AArch64/pow.75.ll b/llvm/test/CodeGen/AArch64/pow.75.ll
index 4d760e13468bc..77fa57dd584a2 100644
--- a/llvm/test/CodeGen/AArch64/pow.75.ll
+++ b/llvm/test/CodeGen/AArch64/pow.75.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=aarch64-- -debug 2>&1 | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
declare float @llvm.pow.f32(float, float)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/AArch64/split-vector-insert.ll b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
index 37e672567103e..5b53de383b6cb 100644
--- a/llvm/test/CodeGen/AArch64/split-vector-insert.ll
+++ b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -debug-only=legalize-types 2>&1 | FileCheck %s --check-prefix=CHECK-LEGALIZATION
; RUN: llc < %s | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
target triple = "aarch64-unknown-linux-gnu"
attributes #0 = {"target-features"="+sve"}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll b/llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
index 94b42f1215b9e..f36cf3ae04c7c 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
@@ -1,5 +1,6 @@
; REQUIRES: arm-registered-target
; REQUIRES: asserts
+; REQUIRES: abi_breaking_checks
; RUN: llc -o /dev/null %s -debug-only=legalize-types 2>&1 | FileCheck %s
; This test check that when v4f64 gets broken down to two v2f64 it maintains
diff --git a/llvm/test/CodeGen/ARM/pow.75.ll b/llvm/test/CodeGen/ARM/pow.75.ll
index 32719f164fb1a..4a191851d40dc 100644
--- a/llvm/test/CodeGen/ARM/pow.75.ll
+++ b/llvm/test/CodeGen/ARM/pow.75.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabihf -mattr=neon -debug 2>&1 | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
declare float @llvm.pow.f32(float, float)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll b/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
index 03dd0b8bbf5ad..eecaf6d723788 100644
--- a/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
+++ b/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; This test validates that ISel picks the correct equivalent of below mentioned intrinsics
; For S2_asr_i_r_rnd_goodsyntax:
diff --git a/llvm/test/CodeGen/Mips/address-selection.ll b/llvm/test/CodeGen/Mips/address-selection.ll
index 5a1a97fdb3528..467f44ff73d6e 100644
--- a/llvm/test/CodeGen/Mips/address-selection.ll
+++ b/llvm/test/CodeGen/Mips/address-selection.ll
@@ -6,7 +6,7 @@
; RUN: llc -march=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \
; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; Tests that the correct ISA is selected for computing a global address.
diff --git a/llvm/test/CodeGen/Mips/cconv/byval.ll b/llvm/test/CodeGen/Mips/cconv/byval.ll
index 5d77107d5966a..81f920943e00e 100644
--- a/llvm/test/CodeGen/Mips/cconv/byval.ll
+++ b/llvm/test/CodeGen/Mips/cconv/byval.ll
@@ -15,7 +15,7 @@
; RUN: llc < %s -mtriple=mips64-linux-gnu -target-abi n64 -verify-machineinstrs \
; RUN: -debug 2>&1 | FileCheck %s --check-prefix=N64-SDAG
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; Test that reserved argument area is shared between the memcpy call and the
; call to f2. This eliminates the nested call sequence nodes.
diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
index cc6a7affcbd4f..0f7c40baa90c4 100644
--- a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
+++ b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; Test that the correct ISA is selected for the materialization of constants.
diff --git a/llvm/test/CodeGen/Mips/frameindex.ll b/llvm/test/CodeGen/Mips/frameindex.ll
index 3f436312e74f7..321e2b84ba1e0 100644
--- a/llvm/test/CodeGen/Mips/frameindex.ll
+++ b/llvm/test/CodeGen/Mips/frameindex.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MM
; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MIPS64
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; CHECK-LABEL: Instruction selection ends:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/isel.ll b/llvm/test/CodeGen/Mips/llvm-ir/isel.ll
index cdcd3fd6876d7..7df19a22460c1 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/isel.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/isel.ll
@@ -1,7 +1,7 @@
; RUN: llc --mtriple=mips-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MIPS
; RUN: llc --mtriple=mips-mti-linux-gnu < %s -mattr=+micromips -debug 2>&1 | FileCheck %s --check-prefixes=CHECK,MM
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; Test that the correct mul instruction is selected upfront.
diff --git a/llvm/test/CodeGen/PowerPC/add_cmp.ll b/llvm/test/CodeGen/PowerPC/add_cmp.ll
index cbe16a498a538..506aa2c6c15f2 100644
--- a/llvm/test/CodeGen/PowerPC/add_cmp.ll
+++ b/llvm/test/CodeGen/PowerPC/add_cmp.ll
@@ -1,10 +1,10 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs -debug 2>&1 | FileCheck %s
define zeroext i1 @addiCmpiUnsigned(i32 zeroext %x) {
entry:
- %add = add nuw i32 10, %x
+ %add = add nuw i32 10, %x
%cmp = icmp ugt i32 %add, 100
ret i1 %cmp
@@ -17,7 +17,7 @@ entry:
define zeroext i1 @addiCmpiSigned(i32 signext %x) {
entry:
- %add = add nsw i32 16, %x
+ %add = add nsw i32 16, %x
%cmp = icmp sgt i32 %add, 30
ret i1 %cmp
@@ -30,7 +30,7 @@ entry:
define zeroext i1 @addiCmpiUnsignedOverflow(i32 zeroext %x) {
entry:
- %add = add nuw i32 110, %x
+ %add = add nuw i32 110, %x
%cmp = icmp ugt i32 %add, 100
ret i1 %cmp
@@ -43,7 +43,7 @@ entry:
define zeroext i1 @addiCmpiSignedOverflow(i16 signext %x) {
entry:
- %add = add nsw i16 16, %x
+ %add = add nsw i16 16, %x
%cmp = icmp sgt i16 %add, -32767
ret i1 %cmp
diff --git a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll
index 5052d3a93e459..1ad50162d9a3d 100644
--- a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll
+++ b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: llc < %s -mtriple=powerpc64le -debug-only=isel -o /dev/null 2>&1 | FileCheck %s --check-prefix=FMFDEBUG
; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s --check-prefix=FMF
; RUN: llc < %s -mtriple=powerpc64le -debug-only=isel -o /dev/null 2>&1 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s --check-prefix=GLOBALDEBUG
diff --git a/llvm/test/CodeGen/PowerPC/pow.75.ll b/llvm/test/CodeGen/PowerPC/pow.75.ll
index 723755ce15466..b605ae429df6d 100644
--- a/llvm/test/CodeGen/PowerPC/pow.75.ll
+++ b/llvm/test/CodeGen/PowerPC/pow.75.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -debug 2>&1 | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
declare float @llvm.pow.f32(float, float)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll b/llvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll
index 4258848ac4270..e677022cf56c7 100644
--- a/llvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll
+++ b/llvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll
@@ -1,6 +1,6 @@
; RUN: llc -verify-machineinstrs -mtriple=s390x-linux-gnu < %s -debug -stop-after=machineverifier 2>&1 | FileCheck %s
+; REQUIRES: asserts, abi_breaking_checks
-; REQUIRES: asserts
define i128 @func1({ i128, i8* } %struct) {
; Verify that we get a combine on the build_pair, creating a LD8 load somewhere
; between "Initial selection DAG" and "Optimized lowered selection DAG".
diff --git a/llvm/test/CodeGen/SystemZ/isel-debug.ll b/llvm/test/CodeGen/SystemZ/isel-debug.ll
index b867dac692879..02128b6c0ac16 100644
--- a/llvm/test/CodeGen/SystemZ/isel-debug.ll
+++ b/llvm/test/CodeGen/SystemZ/isel-debug.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu -debug-only=systemz-isel -o - 2>&1 | \
; RUN: FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
;
; Check that some debug output is printed without problems.
; CHECK: SystemZAddressingMode
diff --git a/llvm/test/CodeGen/VE/Vector/vp_srem.ll b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
index 15a3dcaf288aa..b4ff6bbc022fe 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_srem.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
@@ -1,7 +1,7 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s
-; CHECK: t{{[0-9]+}}: v256i32 = vp_srem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
+; CHECK: t{{[0-9]+}}: v256i32 = vp_srem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
diff --git a/llvm/test/CodeGen/VE/Vector/vp_urem.ll b/llvm/test/CodeGen/VE/Vector/vp_urem.ll
index 5465e9fdb1439..c85a6b0af0bd0 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_urem.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_urem.ll
@@ -1,7 +1,7 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s
-; CHECK: t{{[0-9]+}}: v256i32 = vp_urem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
+; CHECK: t{{[0-9]+}}: v256i32 = vp_urem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
diff --git a/llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll b/llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll
index 4f703d42fdf5f..3aee85a75d788 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll
@@ -1,4 +1,4 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -o /dev/null -debug-only=isel 2>&1 | FileCheck %s
; Make sure we emit the basic block exports and the TokenFactor before the
diff --git a/llvm/test/CodeGen/X86/fmf-propagation.ll b/llvm/test/CodeGen/X86/fmf-propagation.ll
index 07982ae17cf91..7bec69541c0e0 100644
--- a/llvm/test/CodeGen/X86/fmf-propagation.ll
+++ b/llvm/test/CodeGen/X86/fmf-propagation.ll
@@ -1,4 +1,4 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck %s
; This tests the propagation of fast-math-flags from IR instructions to SDNodeFlags.
diff --git a/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll b/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
index 67b399b36220a..dcd27bd7340b7 100644
--- a/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
+++ b/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
@@ -1,4 +1,4 @@
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck -check-prefix=DBGDAG %s
diff --git a/llvm/test/CodeGen/X86/pow.75.ll b/llvm/test/CodeGen/X86/pow.75.ll
index 9f5adb945ae62..f2543ce3ce1d8 100644
--- a/llvm/test/CodeGen/X86/pow.75.ll
+++ b/llvm/test/CodeGen/X86/pow.75.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-- -debug 2>&1 | FileCheck %s
-; REQUIRES: asserts
+; REQUIRES: asserts, abi_breaking_checks
declare float @llvm.pow.f32(float, float)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
diff --git a/llvm/test/lit.cfg.py b/llvm/test/lit.cfg.py
index bacf9960bccc1..379e5fd2e6a9c 100644
--- a/llvm/test/lit.cfg.py
+++ b/llvm/test/lit.cfg.py
@@ -406,6 +406,9 @@ def have_ld64_plugin_support():
if config.expensive_checks:
config.available_features.add('expensive_checks')
+if config.abi_breaking_checks:
+ config.available_features.add('abi_breaking_checks')
+
if "MemoryWithOrigins" in config.llvm_use_sanitizer:
config.available_features.add('use_msan_with_origins')
diff --git a/llvm/test/lit.site.cfg.py.in b/llvm/test/lit.site.cfg.py.in
index 393caff63a375..d64694b61132e 100644
--- a/llvm/test/lit.site.cfg.py.in
+++ b/llvm/test/lit.site.cfg.py.in
@@ -57,6 +57,7 @@ config.have_tf_api = @LLVM_HAVE_TF_API@
config.llvm_inliner_model_autogenerated = @LLVM_INLINER_MODEL_AUTOGENERATED@
config.llvm_raevict_model_autogenerated = @LLVM_RAEVICT_MODEL_AUTOGENERATED@
config.expensive_checks = @LLVM_ENABLE_EXPENSIVE_CHECKS@
+config.abi_breaking_checks = @LLVM_ENABLE_ABI_BREAKING_CHECKS@
import lit.llvm
lit.llvm.initialize(lit_config, config)
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu-isel-support.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu-isel-support.test
index 61c4034c21705..5219513dcd0b5 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu-isel-support.test
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu-isel-support.test
@@ -1,4 +1,5 @@
# REQUIRES: asserts
+# REQUIRES: abi_breaking_checks
# REQUIRES: amdgpu-registered-target
## Basic test checking that update_llc_test_checks.py can update a file with isel debug output
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai-isel-support.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai-isel-support.test
index 945849fc5062f..f194f620cfb04 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai-isel-support.test
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai-isel-support.test
@@ -1,4 +1,5 @@
# REQUIRES: asserts
+# REQUIRES: abi_breaking_checks
# REQUIRES: lanai-registered-target
## Basic test checking that update_llc_test_checks.py can update a file with isel debug output
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-isel-support.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-isel-support.test
index 4ae0e73203b7d..f6441b8f59298 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-isel-support.test
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-isel-support.test
@@ -1,4 +1,5 @@
# REQUIRES: asserts
+# REQUIRES: abi_breaking_checks
# REQUIRES: x86-registered-target
## Basic test checking that update_llc_test_checks.py can update a file with isel debug output
More information about the llvm-commits
mailing list