[llvm] 46776f7 - Fix warnings about variables that are set but only used in debug mode
Martin Storsjö via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 00:02:15 PDT 2022
Author: Martin Storsjö
Date: 2022-04-06T10:01:46+03:00
New Revision: 46776f7556a337ebf210b1cac838bca2aaa15351
URL: https://github.com/llvm/llvm-project/commit/46776f7556a337ebf210b1cac838bca2aaa15351
DIFF: https://github.com/llvm/llvm-project/commit/46776f7556a337ebf210b1cac838bca2aaa15351.diff
LOG: Fix warnings about variables that are set but only used in debug mode
Add void casts to mark the variables used, next to the places where
they are used in assert or `LLVM_DEBUG()` expressions.
Differential Revision: https://reviews.llvm.org/D123117
Added:
Modified:
lld/wasm/InputFiles.cpp
lld/wasm/SyntheticSections.cpp
llvm/lib/Analysis/LoopInfo.cpp
llvm/lib/CodeGen/MIRFSDiscriminator.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/StackColoring.cpp
llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
llvm/lib/Target/X86/X86FastTileConfig.cpp
llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
llvm/lib/Transforms/Scalar/GVN.cpp
llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/DFAEmitter.cpp
llvm/utils/TableGen/GlobalISelEmitter.cpp
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/lld/wasm/InputFiles.cpp b/lld/wasm/InputFiles.cpp
index f887b6158cb10..f6f35376ec424 100644
--- a/lld/wasm/InputFiles.cpp
+++ b/lld/wasm/InputFiles.cpp
@@ -689,6 +689,7 @@ void ArchiveFile::parse() {
++count;
}
LLVM_DEBUG(dbgs() << "Read " << count << " symbols\n");
+ (void) count;
}
void ArchiveFile::addMember(const Archive::Symbol *sym) {
diff --git a/lld/wasm/SyntheticSections.cpp b/lld/wasm/SyntheticSections.cpp
index 7bc9c274ff984..6dde7469f6ee8 100644
--- a/lld/wasm/SyntheticSections.cpp
+++ b/lld/wasm/SyntheticSections.cpp
@@ -589,6 +589,7 @@ void ElemSection::writeBody() {
uint32_t tableIndex = config->tableBase;
for (const FunctionSymbol *sym : indirectFunctions) {
assert(sym->getTableIndex() == tableIndex);
+ (void) tableIndex;
writeUleb128(os, sym->getFunctionIndex(), "function index");
++tableIndex;
}
diff --git a/llvm/lib/Analysis/LoopInfo.cpp b/llvm/lib/Analysis/LoopInfo.cpp
index 293c22a3d1f23..7d46e1c28df34 100644
--- a/llvm/lib/Analysis/LoopInfo.cpp
+++ b/llvm/lib/Analysis/LoopInfo.cpp
@@ -736,6 +736,7 @@ void UnloopUpdater::updateBlockParents() {
bool Changed = FoundIB;
for (unsigned NIters = 0; Changed; ++NIters) {
assert(NIters < Unloop.getNumBlocks() && "runaway iterative algorithm");
+ (void) NIters;
// Iterate over the postorder list of blocks, propagating the nearest loop
// from successors to predecessors as before.
diff --git a/llvm/lib/CodeGen/MIRFSDiscriminator.cpp b/llvm/lib/CodeGen/MIRFSDiscriminator.cpp
index 90b1725802d9a..3152102410d78 100644
--- a/llvm/lib/CodeGen/MIRFSDiscriminator.cpp
+++ b/llvm/lib/CodeGen/MIRFSDiscriminator.cpp
@@ -135,6 +135,7 @@ bool MIRAddFSDiscriminators::runOnMachineFunction(MachineFunction &MF) {
if (Changed) {
createFSDiscriminatorVariable(MF.getFunction().getParent());
LLVM_DEBUG(dbgs() << "Num of FS Discriminators: " << NumNewD << "\n");
+ (void) NumNewD;
}
return Changed;
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 93be8f689d573..8c262130fb70d 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -847,6 +847,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
while (!PBQPAllocComplete) {
LLVM_DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
+ (void) Round;
PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
initializeGraph(G, VRM, *VRegSpiller);
diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp
index 2a59b12871f98..de549eff1787b 100644
--- a/llvm/lib/CodeGen/StackColoring.cpp
+++ b/llvm/lib/CodeGen/StackColoring.cpp
@@ -1143,6 +1143,9 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) {
LLVM_DEBUG(dbgs() << "Fixed " << FixedMemOp << " machine memory operands.\n");
LLVM_DEBUG(dbgs() << "Fixed " << FixedDbg << " debug locations.\n");
LLVM_DEBUG(dbgs() << "Fixed " << FixedInstr << " machine instructions.\n");
+ (void) FixedMemOp;
+ (void) FixedDbg;
+ (void) FixedInstr;
}
void StackColoring::removeInvalidSlotRanges() {
diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
index 4cdf5f144437f..37a65b64a885b 100644
--- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
@@ -223,6 +223,7 @@ AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
if (isFirstInstructionInSequence(PrevInstr) &&
isSecondInstructionInSequence(CurrInstr)) {
LLVM_DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n");
+ (void) Idx;
Sequences.push_back(CurrInstr);
}
}
diff --git a/llvm/lib/Target/X86/X86FastTileConfig.cpp b/llvm/lib/Target/X86/X86FastTileConfig.cpp
index 061fff50bcea0..5ff848243e433 100644
--- a/llvm/lib/Target/X86/X86FastTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86FastTileConfig.cpp
@@ -154,6 +154,7 @@ MachineInstr *X86FastTileConfig::getKeyAMXInstr(MachineInstr *MI) {
if (isAMXInstr(*II)) {
assert((KeyAMXNum == 0) && "Too many Key AMX instruction!");
+ (void) KeyAMXNum;
KeyAMXNum++;
KeyMI = &*II;
}
diff --git a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
index d421894037f4f..b9fc0cec9c453 100644
--- a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
+++ b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
@@ -1457,6 +1457,7 @@ void PGOUseFunc::populateCounters() {
}
LLVM_DEBUG(dbgs() << "Populate counts in " << NumPasses << " passes.\n");
+ (void) NumPasses;
#ifndef NDEBUG
// Assert every BB has a valid counter.
for (auto &BB : F) {
diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp
index b3c19eeedf4f0..e0d78c944edbe 100644
--- a/llvm/lib/Transforms/Scalar/GVN.cpp
+++ b/llvm/lib/Transforms/Scalar/GVN.cpp
@@ -2593,6 +2593,7 @@ bool GVNPass::runImpl(Function &F, AssumptionCache &RunAC, DominatorTree &RunDT,
unsigned Iteration = 0;
while (ShouldContinue) {
LLVM_DEBUG(dbgs() << "GVN iteration: " << Iteration << "\n");
+ (void) Iteration;
ShouldContinue = iterateOnFunction(F);
Changed |= ShouldContinue;
++Iteration;
diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
index 9d7ea43629d8b..970462fae502a 100644
--- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
+++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
@@ -2087,6 +2087,7 @@ static void relocationViaAlloca(
assert(PromotableAllocas.size() == Live.size() + NumRematerializedValues &&
"we must have the same allocas with lives");
+ (void) NumRematerializedValues;
if (!PromotableAllocas.empty()) {
// Apply mem2reg to promote alloca to SSA
PromoteMemToReg(PromotableAllocas, DT);
diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
index 3b0bd86a78a5a..71cce3e792b76 100644
--- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
@@ -870,6 +870,7 @@ void SimplifyIndvar::simplifyUsers(PHINode *CurrIV, IVVisitor *V) {
Instruction *IVOperand = UseOper.second;
for (unsigned N = 0; IVOperand; ++N) {
assert(N <= Simplified.size() && "runaway iteration");
+ (void) N;
Value *NewOper = foldIVUser(UseInst, IVOperand);
if (!NewOper)
diff --git a/llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp b/llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
index 4a69f96a597a2..7deeaef40cafc 100644
--- a/llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
+++ b/llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
@@ -338,6 +338,7 @@ int main(int argc, char *argv[]) {
assert(TLIandSDKboth + TLIandSDKneither + TLIdoesSDKdoesnt +
TLIdoesntSDKdoes ==
LibFunc::NumLibFuncs);
+ (void) TLIandSDKneither;
outs() << "<< Total TLI yes SDK no: " << TLIdoesSDKdoesnt
<< "\n>> Total TLI no SDK yes: " << TLIdoesntSDKdoes
<< "\n== Total TLI yes SDK yes: " << TLIandSDKboth;
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 073e43a2fc03b..65bcd6fb1e190 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1814,6 +1814,7 @@ void CodeGenRegBank::computeRegUnitWeights() {
unsigned NumIters = 0;
for (bool Changed = true; Changed; ++NumIters) {
assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
+ (void) NumIters;
Changed = false;
for (auto &Reg : Registers) {
CodeGenRegister::RegUnitList NormalUnits;
diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp
index aa3327ab0cb31..f2d9165c5c8c8 100644
--- a/llvm/utils/TableGen/DFAEmitter.cpp
+++ b/llvm/utils/TableGen/DFAEmitter.cpp
@@ -305,6 +305,7 @@ void Automaton::emit(raw_ostream &OS) {
}
LLVM_DEBUG(dbgs() << " NFA automaton has " << SeenStates.size()
<< " states with " << NumTransitions << " transitions.\n");
+ (void) NumTransitions;
const auto &ActionTypes = Transitions.back().getTypes();
OS << "// The type of an action in the " << Name << " automaton.\n";
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 751c06ff95143..707a3641126c1 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -5534,6 +5534,7 @@ std::vector<Matcher *> GlobalISelEmitter::optimizeRules(
ProcessCurrentGroup();
LLVM_DEBUG(dbgs() << "NumGroups: " << NumGroups << "\n");
+ (void) NumGroups;
assert(CurrentGroup->empty() && "The last group wasn't properly processed");
return OptRules;
}
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 8a9ce15c3508b..cafe233005c6d 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -753,7 +753,7 @@ RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
}
OS << " };\n\n";
- OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
+ OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n"
<< " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
if (Rows.size() > 1)
OS << " return Rows[RowMap[IdxA]][IdxB];\n";
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