[llvm] 634bf82 - MachineVerifier: Diagnose undef set on full register defs
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 5 19:33:21 PDT 2022
Author: Matt Arsenault
Date: 2022-04-05T22:19:17-04:00
New Revision: 634bf829a8d289371d5b5a50b787596124228898
URL: https://github.com/llvm/llvm-project/commit/634bf829a8d289371d5b5a50b787596124228898
DIFF: https://github.com/llvm/llvm-project/commit/634bf829a8d289371d5b5a50b787596124228898.diff
LOG: MachineVerifier: Diagnose undef set on full register defs
An undef def of a full register would assert in LiveIntervalCalc.
Added:
llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
Modified:
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 2086157f6434f..47fad5cd0697a 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1913,6 +1913,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
if (MRI->tracksLiveness() && !MI->isDebugInstr())
checkLiveness(MO, MONum);
+ if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
+ MO->getReg().isVirtual()) // TODO: Apply to physregs too
+ report("Undef virtual register def operands require a subregister", MO, MONum);
+
// Verify the consistency of tied operands.
if (MO->isTied()) {
unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
index 34ab58a40f81d..64d27da22d695 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -514,7 +514,7 @@ body: |
# CHECK-LABEL: name: test15_undef_op
# CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x1, $x8
-# CHECK: undef renamable $x10, $x11 = LDPXi renamable $x0, 0 :: (load (s64))
+# CHECK: renamable $x10, $x11 = LDPXi renamable $x0, 0 :: (load (s64))
# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 1 :: (load (s64))
# CHECK-NEXT: STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
# CHECK-NEXT: renamable $x10 = ADDXrr $x10, $x10
@@ -535,7 +535,7 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $x0, $x1, $x8
- renamable undef $x10, renamable $x9 = LDPXi renamable $x0, 0 :: (load (s64))
+ renamable $x10, renamable $x9 = LDPXi renamable $x0, 0 :: (load (s64))
STRXui renamable killed $x9, renamable $x0, 11 :: (store (s64), align 4)
renamable $x9 = LDRXui renamable $x0, 1 :: (load (s64))
STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
index b91d558e7d96b..279f166df6f89 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
@@ -200,53 +200,53 @@ body: |
$edi = MOV32ri 2
CMP32ri8 killed $eax, 2, implicit-def $eflags, debug-location !26
JCC_1 %bb.2.if.end, 5, implicit $eflags
-
+
bb.1.if.else:
successors: %bb.2.if.end(0)
liveins: $rsi
-
+
DBG_VALUE $rsi, _, !13, !20, debug-location !22
$rdi = MOV64rm killed $rsi, 1, _, 8, _, debug-location !27 :: (load (s64) from %ir.arrayidx, !tbaa !28)
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !32
CALL64pcrel32 @atoi, csr_64, implicit $rsp, implicit $rdi, implicit $al, implicit-def $rsp, implicit-def $eax, debug-location !32
$edi = MOV32rr $eax, debug-location !32
DBG_VALUE $edi, _, !14, !20, debug-location !33
-
+
bb.2.if.end:
successors: %bb.3.if.then.3(16), %bb.4.if.else.5(16)
liveins: $edi
-
+
CALL64pcrel32 @change, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !34
$ebx = MOV32rr $eax, debug-location !34
DBG_VALUE $ebx, _, !14, !20, debug-location !33
CMP32ri8 $ebx, 11, implicit-def $eflags, debug-location !37
JCC_1 %bb.4.if.else.5, 12, implicit killed $eflags, debug-location !37
-
+
bb.3.if.then.3:
successors: %bb.5.if.end.7(0)
liveins: $ebx
-
+
DBG_VALUE $ebx, _, !14, !20, debug-location !33
$edi = MOV32rr $ebx, debug-location !38
CALL64pcrel32 @modify, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !38
$ecx = MOV32rr $eax, debug-location !38
$ecx = ADD32rr killed $ecx, killed $ebx, implicit-def dead $eflags, debug-location !40
JMP_1 %bb.5.if.end.7
-
+
bb.4.if.else.5:
successors: %bb.5.if.end.7(0)
liveins: $ebx
-
+
DBG_VALUE $ebx, _, !14, !20, debug-location !33
$edi = MOV32rr killed $ebx, debug-location !42
CALL64pcrel32 @inc, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !42
$ecx = MOV32rr $eax, debug-location !42
-
+
bb.5.if.end.7:
liveins: $ecx
-
+
MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store (s32) into @m, !tbaa !44)
- dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
+ dead $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47
$esi = MOV32rr killed $ecx, debug-location !46
CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46
diff --git a/llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir b/llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
new file mode 100644
index 0000000000000..dc5b467aa73c7
--- /dev/null
+++ b/llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
@@ -0,0 +1,16 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
+
+---
+name: undef_reg_def
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK: *** Bad machine code: Undef virtual register def operands require a subregister ***
+ undef %0:sreg_64 = S_MOV_B64 0
+
+ ; CHECK: *** Bad machine code: Undef virtual register def operands require a subregister ***
+ S_NOP 0, implicit-def undef %1:sreg_64
+ S_ENDPGM 0, implicit %0.sub0, implicit %0.sub1
+
+...
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