[PATCH] D123171: AMDGPU: Handle private atomics

[Matt Arsenault via Phabricator via llvm-commits]

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Use new NotAtomic expansion to turn these into the equivalent
non-atomic operations. Independent lanes cannot access the private
memory of other lanes, so there's no possibility for synchronization.

      

These don't really appear directly in user code, but
InferAddressSpaces can make these appear after optimizations.

      

Fixes issues 54693 and 54274.


https://reviews.llvm.org/D123171

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll

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