[PATCH] D123077: [BOLT][NFC] Move isADD64rr and isADDri out of MCPlusBuilder class

Amir Ayupov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 5 14:32:14 PDT 2022


This revision was automatically updated to reflect the committed changes.
Closed by commit rGf99398fe0ee9: [BOLT][NFC] Move isADD64rr and isADDri out of MCPlusBuilder class (authored by Amir).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123077/new/

https://reviews.llvm.org/D123077

Files:
  bolt/include/bolt/Core/MCPlusBuilder.h
  bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
  bolt/lib/Target/X86/X86MCPlusBuilder.cpp


Index: bolt/lib/Target/X86/X86MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -68,6 +68,13 @@
   return Inst.getOpcode() == X86::MOVSX64rm32;
 }
 
+bool isADD64rr(const MCInst &Inst) { return Inst.getOpcode() == X86::ADD64rr; }
+
+bool isADDri(const MCInst &Inst) {
+  return Inst.getOpcode() == X86::ADD64ri32 ||
+         Inst.getOpcode() == X86::ADD64ri8;
+}
+
 class X86MCPlusBuilder : public MCPlusBuilder {
 public:
   X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info,
@@ -292,19 +299,10 @@
     return 0;
   }
 
-  bool isADD64rr(const MCInst &Inst) const override {
-    return Inst.getOpcode() == X86::ADD64rr;
-  }
-
   bool isSUB(const MCInst &Inst) const override {
     return X86::isSUB(Inst.getOpcode());
   }
 
-  bool isADDri(const MCInst &Inst) const {
-    return Inst.getOpcode() == X86::ADD64ri32 ||
-           Inst.getOpcode() == X86::ADD64ri8;
-  }
-
   bool isLEA64r(const MCInst &Inst) const override {
     return Inst.getOpcode() == X86::LEA64r;
   }
Index: bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -1103,8 +1103,6 @@
 
   bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
 
-  bool isADD64rr(const MCInst &Inst) const override { return false; }
-
   bool isLeave(const MCInst &Inst) const override { return false; }
 
   bool isPop(const MCInst &Inst) const override { return false; }
Index: bolt/include/bolt/Core/MCPlusBuilder.h
===================================================================
--- bolt/include/bolt/Core/MCPlusBuilder.h
+++ bolt/include/bolt/Core/MCPlusBuilder.h
@@ -511,11 +511,6 @@
     return 0;
   }
 
-  virtual bool isADD64rr(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
-
   virtual bool isSUB(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D123077.420638.patch
Type: text/x-patch
Size: 2153 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220405/59993f13/attachment.bin>


More information about the llvm-commits mailing list