[llvm] 82bd0bd - [AArch64] Make PMMIR_EL1 read-only.

[Simon Tatham via llvm-commits]

Author: Simon Tatham
Date: 2022-04-05T11:09:56+01:00
New Revision: 82bd0bd24f61c914f1812646b281c1d0960df0bf

URL: https://github.com/llvm/llvm-project/commit/82bd0bd24f61c914f1812646b281c1d0960df0bf
DIFF: https://github.com/llvm/llvm-project/commit/82bd0bd24f61c914f1812646b281c1d0960df0bf.diff

LOG: [AArch64] Make PMMIR_EL1 read-only.

The Arm architecture reference manual (ARM DDI 0487H.a section
D13.5.12) lists every field in the register as RO, and does not list
an MSR instruction that writes it. So we should be defining it as an
ROSysReg, not an RWSysReg.

Reviewed By: vhscampos

Differential Revision: https://reviews.llvm.org/D123111

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/test/MC/AArch64/basic-a64-diagnostics.s
    llvm/test/MC/AArch64/basic-a64-instructions.s
    llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index cce5813fe6e9d..d715152553578 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -631,6 +631,7 @@ def : ROSysReg<"OSLSR_EL1",          0b10, 0b000, 0b0001, 0b0001, 0b100>;
 def : ROSysReg<"DBGAUTHSTATUS_EL1",  0b10, 0b000, 0b0111, 0b1110, 0b110>;
 def : ROSysReg<"PMCEID0_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b110>;
 def : ROSysReg<"PMCEID1_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b111>;
+def : ROSysReg<"PMMIR_EL1",          0b11, 0b000, 0b1001, 0b1110, 0b110>;
 def : ROSysReg<"MIDR_EL1",           0b11, 0b000, 0b0000, 0b0000, 0b000>;
 def : ROSysReg<"CCSIDR_EL1",         0b11, 0b001, 0b0000, 0b0000, 0b000>;
 
@@ -977,7 +978,6 @@ def : RWSysReg<"PMUSERENR_EL0",      0b11, 0b011, 0b1001, 0b1110, 0b000>;
 def : RWSysReg<"PMINTENSET_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b001>;
 def : RWSysReg<"PMINTENCLR_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b010>;
 def : RWSysReg<"PMOVSSET_EL0",       0b11, 0b011, 0b1001, 0b1110, 0b011>;
-def : RWSysReg<"PMMIR_EL1",          0b11, 0b000, 0b1001, 0b1110, 0b110>;
 def : RWSysReg<"MAIR_EL1",           0b11, 0b000, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL2",           0b11, 0b100, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL3",           0b11, 0b110, 0b1010, 0b0010, 0b000>;

diff  --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index 00242f471d0cf..21aa4ff627318 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -3605,6 +3605,7 @@
         msr ID_AA64MMFR1_EL1, x12
         msr PMCEID0_EL0, x12
         msr PMCEID1_EL0, x12
+        msr PMMIR_EL1, x12
         msr RVBAR_EL1, x12
         msr RVBAR_EL2, x12
         msr RVBAR_EL3, x12
@@ -3749,6 +3750,9 @@
 // CHECK-ERROR-NEXT:         msr PMCEID1_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr PMMIR_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr RVBAR_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate

diff  --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index f946ac284fcd1..02ceb9cad6923 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -3834,7 +3834,6 @@ _func:
 	msr PMINTENSET_EL1, x12
 	msr PMINTENCLR_EL1, x12
 	msr PMOVSSET_EL0, x12
-	msr PMMIR_EL1, x12
 	msr MAIR_EL1, x12
 	msr MAIR_EL2, x12
 	msr MAIR_EL3, x12
@@ -4086,7 +4085,6 @@ _func:
 // CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12        // encoding: [0x2c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12        // encoding: [0x4c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12          // encoding: [0x6c,0x9e,0x1b,0xd5]
-// CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12        // encoding: [0xcc,0x9e,0x18,0xd5]
 // CHECK: msr      {{mair_el1|MAIR_EL1}}, x12              // encoding: [0x0c,0xa2,0x18,0xd5]
 // CHECK: msr      {{mair_el2|MAIR_EL2}}, x12              // encoding: [0x0c,0xa2,0x1c,0xd5]
 // CHECK: msr      {{mair_el3|MAIR_EL3}}, x12              // encoding: [0x0c,0xa2,0x1e,0xd5]

diff  --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 557883bc244ec..15d03cdcaa297 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3308,7 +3308,6 @@
 # CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12
 # CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
 # CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12
-# CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12
 # CHECK: msr      {{mair_el1|MAIR_EL1}}, x12
 # CHECK: msr      {{mair_el2|MAIR_EL2}}, x12
 # CHECK: msr      {{mair_el3|MAIR_EL3}}, x12
@@ -3604,7 +3603,6 @@
 # CHECK: mrs      x9, {{pmintenset_el1|PMINTENSET_EL1}}
 # CHECK: mrs      x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
 # CHECK: mrs      x9, {{pmovsset_el0|PMOVSSET_EL0}}
-# CHECK: mrs      x9, {{pmmir_el1|PMMIR_EL1}}
 # CHECK: mrs      x9, {{mair_el1|MAIR_EL1}}
 # CHECK: mrs      x9, {{mair_el2|MAIR_EL2}}
 # CHECK: mrs      x9, {{mair_el3|MAIR_EL3}}