[PATCH] D122796: [SVE][AArch64] Enable first active true vector combine for INTRINSIC_WO_CHAIN

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

Whether it's worth having the CC restriction aside, the patch look good to me.  I've mentioned some refactoring to consider.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14509
 
   SDValue SetCC = N->getOperand(0);
   EVT VT = SetCC.getValueType();
----------------
This name is less meaningful after this change.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14518-14521
+  if ((SetCC.getOpcode() != ISD::SETCC) &&
+      !(SetCC.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
+        (SetCC.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilelo ||
+         SetCC.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilels)))
----------------
Perhaps it's worth extracting this into a `isPredicateCCSettingOp` helper function (or lambda) as eventually we'll want to add all such operations if we're going to persist with this restriction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122796/new/

https://reviews.llvm.org/D122796