[llvm] 623d4b5 - [X86] Support optional NOT stages in the AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) fold

[Roman Lebedev via llvm-commits]

Thanks!

On Mon, Apr 4, 2022 at 12:57 PM Simon Pilgrim via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
>
> Author: Simon Pilgrim
> Date: 2022-04-04T10:51:26+01:00
> New Revision: 623d4b57873df98ffad852462cf292601e79fb93
>
> URL: https://github.com/llvm/llvm-project/commit/623d4b57873df98ffad852462cf292601e79fb93
> DIFF: https://github.com/llvm/llvm-project/commit/623d4b57873df98ffad852462cf292601e79fb93.diff
>
> LOG: [X86] Support optional NOT stages in the AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) fold
>
> Extension to D122891, peek through NOT() ops, adjusting the condcode as we go.
>
> Added:
>
>
> Modified:
>     llvm/lib/Target/X86/X86ISelLowering.cpp
>     llvm/test/CodeGen/X86/setcc.ll
>
> Removed:
>
>
>
> ################################################################################
> diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
> index 4ba32bd578539..5bd5546651f60 100644
> --- a/llvm/lib/Target/X86/X86ISelLowering.cpp
> +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
> @@ -47338,9 +47338,24 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
>              Src.getOpcode() == ISD::TRUNCATE) &&
>             Src.getOperand(0)->hasOneUse())
>        Src = Src.getOperand(0);
> -    if (Src.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(Src.getOperand(1)))
> -      if (SDValue BT = getBT(Src.getOperand(0), Src.getOperand(1), dl, DAG))
> -        return DAG.getZExtOrTrunc(getSETCC(X86::COND_B, BT, dl, DAG), dl, VT);
> +    X86::CondCode X86CC = X86::COND_B;
> +    // Peek through AND(NOT(SRL(X,Y)),1).
> +    if (isBitwiseNot(Src)) {
> +      Src = Src.getOperand(0);
> +      X86CC = X86::COND_AE;
> +    }
> +    if (Src.getOpcode() == ISD::SRL &&
> +        !isa<ConstantSDNode>(Src.getOperand(1))) {
> +      SDValue BitNo = Src.getOperand(1);
> +      Src = Src.getOperand(0);
> +      // Peek through AND(SRL(NOT(X),Y),1).
> +      if (isBitwiseNot(Src)) {
> +        Src = Src.getOperand(0);
> +        X86CC = X86CC == X86::COND_AE ? X86::COND_B : X86::COND_AE;
> +      }
> +      if (SDValue BT = getBT(Src, BitNo, dl, DAG))
> +        return DAG.getZExtOrTrunc(getSETCC(X86CC, BT, dl, DAG), dl, VT);
> +    }
>    }
>
>    if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
>
> diff  --git a/llvm/test/CodeGen/X86/setcc.ll b/llvm/test/CodeGen/X86/setcc.ll
> index f538069ae2282..03efa5515686b 100644
> --- a/llvm/test/CodeGen/X86/setcc.ll
> +++ b/llvm/test/CodeGen/X86/setcc.ll
> @@ -205,21 +205,18 @@ define i64 @t9(i32 %0, i32 %1) {
>  define i32 @t10(i32 %0, i32 %1) {
>  ; X86-LABEL: t10:
>  ; X86:       ## %bb.0:
> -; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
> -; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
> -; X86-NEXT:    shrl %cl, %eax
> -; X86-NEXT:    notl %eax
> -; X86-NEXT:    andl $1, %eax
> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
> +; X86-NEXT:    xorl %eax, %eax
> +; X86-NEXT:    btl %edx, %ecx
> +; X86-NEXT:    setae %al
>  ; X86-NEXT:    retl
>  ;
>  ; X64-LABEL: t10:
>  ; X64:       ## %bb.0:
> -; X64-NEXT:    movl %esi, %ecx
> -; X64-NEXT:    movl %edi, %eax
> -; X64-NEXT:    ## kill: def $cl killed $cl killed $ecx
> -; X64-NEXT:    shrl %cl, %eax
> -; X64-NEXT:    notl %eax
> -; X64-NEXT:    andl $1, %eax
> +; X64-NEXT:    xorl %eax, %eax
> +; X64-NEXT:    btl %esi, %edi
> +; X64-NEXT:    setae %al
>  ; X64-NEXT:    retq
>    %3 = lshr i32 %0, %1
>    %4 = and i32 %3, 1
> @@ -231,19 +228,17 @@ define i32 @t11(i32 %0, i32 %1) {
>  ; X86-LABEL: t11:
>  ; X86:       ## %bb.0:
>  ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
> -; X86-NEXT:    notl %ecx
>  ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
>  ; X86-NEXT:    xorl %eax, %eax
>  ; X86-NEXT:    btl %edx, %ecx
> -; X86-NEXT:    setb %al
> +; X86-NEXT:    setae %al
>  ; X86-NEXT:    retl
>  ;
>  ; X64-LABEL: t11:
>  ; X64:       ## %bb.0:
> -; X64-NEXT:    notl %edi
>  ; X64-NEXT:    xorl %eax, %eax
>  ; X64-NEXT:    btl %esi, %edi
> -; X64-NEXT:    setb %al
> +; X64-NEXT:    setae %al
>  ; X64-NEXT:    retq
>    %3 = xor i32 %0, -1
>    %4 = lshr i32 %3, %1
> @@ -254,23 +249,18 @@ define i32 @t11(i32 %0, i32 %1) {
>  define i32 @t12(i32 %0, i32 %1) {
>  ; X86-LABEL: t12:
>  ; X86:       ## %bb.0:
> -; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
> -; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
> -; X86-NEXT:    notl %eax
> -; X86-NEXT:    shrl %cl, %eax
> -; X86-NEXT:    notl %eax
> -; X86-NEXT:    andl $1, %eax
> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
> +; X86-NEXT:    xorl %eax, %eax
> +; X86-NEXT:    btl %edx, %ecx
> +; X86-NEXT:    setb %al
>  ; X86-NEXT:    retl
>  ;
>  ; X64-LABEL: t12:
>  ; X64:       ## %bb.0:
> -; X64-NEXT:    movl %esi, %ecx
> -; X64-NEXT:    movl %edi, %eax
> -; X64-NEXT:    notl %eax
> -; X64-NEXT:    ## kill: def $cl killed $cl killed $ecx
> -; X64-NEXT:    shrl %cl, %eax
> -; X64-NEXT:    notl %eax
> -; X64-NEXT:    andl $1, %eax
> +; X64-NEXT:    xorl %eax, %eax
> +; X64-NEXT:    btl %esi, %edi
> +; X64-NEXT:    setb %al
>  ; X64-NEXT:    retq
>    %3 = xor i32 %0, -1
>    %4 = lshr i32 %3, %1
>
>
>
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