[PATCH] D122212: [RISCV] Add zbkb feature for zext.h Instruction

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added a comment.

In D122212#3419632 <https://reviews.llvm.org/D122212#3419632>, @craig.topper wrote:

> In D122212#3418598 <https://reviews.llvm.org/D122212#3418598>, @Miss_Grape wrote:
>
>> In D122212#3399915 <https://reviews.llvm.org/D122212#3399915>, @craig.topper wrote:
>>
>>> The correct fix is to change the predicate here to include Zbkb
>>>
>>>   let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {                                
>>>   def ZEXT_H_RV32 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP, "zext.h">,         
>>>                     Sched<[WriteIALU, ReadIALU]>;                                  
>>>   } // Predicates = [HasStdExtZbbOrZbp, IsRV32]                                    
>>>                                                                                    
>>>   let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {                                
>>>   def ZEXT_H_RV64 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP_32, "zext.h">,      
>>>                     Sched<[WriteIALU, ReadIALU]>;                                  
>>>   } // Predicates = [HasStdExtZbbOrZbp, IsRV64] 
>>
>> Can you send me the Bitmap manual you read, I read the riscv-crypto-spec-scalar-v1.0.1.pdf , and zext.h does not belong to zbkb
>> zbkb Instruction：
>> F22605625: image.png <https://reviews.llvm.org/F22605625>
>
> The zext.h encoding is a subset of the pack encodings. We need to have consistent behavior in when we use the two instruction representations. Otherwise disassembling with Zbb and Zbkb both enabled becomes ambiguous.

Fixed


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122212/new/

https://reviews.llvm.org/D122212