[PATCH] D122963: [X86] Always extend the integer arguments of callee.

[LiuChen via Phabricator via llvm-commits]

LiuChen3 created this revision.
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This patch is based on the D71178 <https://reviews.llvm.org/D71178>.
We have disscussion here:
https://discourse.llvm.org/t/always-extend-the-integer-parameters-of-callee/61319.

We want to make clang behave just like gcc to avoid compatibility issues
between different compilers. We can't remove `zeroext/signext` on the front-end,
which will cause compatibility issues between the new clang and the previous clang.

There are many test cases waiting to be fixed. I put this patch here to see if
we can do this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122963

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/callee-extend.ll


Index: llvm/test/CodeGen/X86/callee-extend.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/callee-extend.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; Ignore the zeroext/signext attribute and always do sign/zero extension in the callee.
+; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s
+
+define i64 @calleeu8(i8 noundef zeroext %a) nounwind {
+; CHECK-LABEL: calleeu8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    retq
+entry:
+  %conv = zext i8 %a to i64
+  ret i64 %conv
+}
+
+define i64 @calleeu16(i16 noundef zeroext %a) nounwind {
+; CHECK-LABEL: calleeu16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
+entry:
+  %conv = zext i16 %a to i64
+  ret i64 %conv
+}
+
+define i64 @callees8(i8 noundef signext %a) nounwind {
+; CHECK-LABEL: callees8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    movsbq %dil, %rax
+; CHECK-NEXT:    retq
+entry:
+  %conv = sext i8 %a to i64
+  ret i64 %conv
+}
+
+define i64 @callees16(i16 noundef signext %a) nounwind {
+; CHECK-LABEL: callees16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    movswq %di, %rax
+; CHECK-NEXT:    retq
+entry:
+  %conv = sext i16 %a to i64
+  ret i64 %conv
+}
+
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3946,16 +3946,7 @@
         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
       }
 
-      // If this is an 8 or 16-bit value, it is really passed promoted to 32
-      // bits.  Insert an assert[sz]ext to capture this, then truncate to the
-      // right size.
-      if (VA.getLocInfo() == CCValAssign::SExt)
-        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
-                               DAG.getValueType(VA.getValVT()));
-      else if (VA.getLocInfo() == CCValAssign::ZExt)
-        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
-                               DAG.getValueType(VA.getValVT()));
-      else if (VA.getLocInfo() == CCValAssign::BCvt)
+      if (VA.getLocInfo() == CCValAssign::BCvt)
         ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
 
       if (VA.isExtInLoc()) {


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