[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll:1081
+; CHECK-ASM-NEXT:    lb a4, 0(a0)
+; CHECK-ASM-NEXT:    mv a5, a2
+; CHECK-ASM-NEXT:    addw a2, a4, a3
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craig.topper wrote:
> This move is interesting. I'll look closer at that.
D122933 should fix the mv here.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll:1077
+; CHECK-ASM-NEXT:    add a3, a4, a3
+; CHECK-ASM-NEXT:    add a1, a1, a3
 ; CHECK-ASM-NEXT:  .LBB12_6: # =>This Inner Loop Header: Depth=1
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jrtc27 wrote:
> This is a regression
This does save an add inside the loop.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735