[llvm] 31b8a1d - [RISCV] Add tests for uaddo with a constant 1. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 1 12:32:05 PDT 2022
Author: Craig Topper
Date: 2022-04-01T12:29:08-07:00
New Revision: 31b8a1dc46d216475c14be534f06ec2ab201640f
URL: https://github.com/llvm/llvm-project/commit/31b8a1dc46d216475c14be534f06ec2ab201640f
DIFF: https://github.com/llvm/llvm-project/commit/31b8a1dc46d216475c14be534f06ec2ab201640f.diff
LOG: [RISCV] Add tests for uaddo with a constant 1. NFC
The overflow calculation can be optimized to check if the add
result is 0.
Added:
Modified:
llvm/test/CodeGen/RISCV/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 8e5cb87d1df80..473ea4040bf84 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -424,6 +424,44 @@ entry:
ret i1 %obit
}
+define zeroext i1 @uaddo.i32.constant_one(i32 %v1, i32* %res) {
+; RV32-LABEL: uaddo.i32.constant_one:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi a2, a0, 1
+; RV32-NEXT: sltu a0, a2, a0
+; RV32-NEXT: sw a2, 0(a1)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: uaddo.i32.constant_one:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: sext.w a2, a0
+; RV64-NEXT: addiw a3, a0, 1
+; RV64-NEXT: sltu a0, a3, a2
+; RV64-NEXT: sw a3, 0(a1)
+; RV64-NEXT: ret
+;
+; RV32ZBA-LABEL: uaddo.i32.constant_one:
+; RV32ZBA: # %bb.0: # %entry
+; RV32ZBA-NEXT: addi a2, a0, 1
+; RV32ZBA-NEXT: sltu a0, a2, a0
+; RV32ZBA-NEXT: sw a2, 0(a1)
+; RV32ZBA-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i32.constant_one:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sext.w a2, a0
+; RV64ZBA-NEXT: addiw a3, a0, 1
+; RV64ZBA-NEXT: sltu a0, a3, a2
+; RV64ZBA-NEXT: sw a3, 0(a1)
+; RV64ZBA-NEXT: ret
+entry:
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: uaddo.i64:
; RV32: # %bb.0: # %entry
@@ -431,10 +469,10 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: beq a3, a1, .LBB9_2
+; RV32-NEXT: beq a3, a1, .LBB10_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a3, a1
-; RV32-NEXT: .LBB9_2: # %entry
+; RV32-NEXT: .LBB10_2: # %entry
; RV32-NEXT: sw a2, 0(a4)
; RV32-NEXT: sw a3, 4(a4)
; RV32-NEXT: ret
@@ -452,10 +490,10 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32ZBA-NEXT: add a2, a0, a2
; RV32ZBA-NEXT: sltu a0, a2, a0
; RV32ZBA-NEXT: add a3, a3, a0
-; RV32ZBA-NEXT: beq a3, a1, .LBB9_2
+; RV32ZBA-NEXT: beq a3, a1, .LBB10_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a3, a1
-; RV32ZBA-NEXT: .LBB9_2: # %entry
+; RV32ZBA-NEXT: .LBB10_2: # %entry
; RV32ZBA-NEXT: sw a2, 0(a4)
; RV32ZBA-NEXT: sw a3, 4(a4)
; RV32ZBA-NEXT: ret
@@ -474,6 +512,56 @@ entry:
ret i1 %obit
}
+define zeroext i1 @uaddo.i64.constant_one(i64 %v1, i64* %res) {
+; RV32-LABEL: uaddo.i64.constant_one:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: mv a3, a0
+; RV32-NEXT: addi a4, a0, 1
+; RV32-NEXT: sltu a0, a4, a0
+; RV32-NEXT: add a5, a1, a0
+; RV32-NEXT: bgeu a4, a3, .LBB11_2
+; RV32-NEXT: # %bb.1: # %entry
+; RV32-NEXT: sltu a0, a5, a1
+; RV32-NEXT: .LBB11_2: # %entry
+; RV32-NEXT: sw a4, 0(a2)
+; RV32-NEXT: sw a5, 4(a2)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: uaddo.i64.constant_one:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: addi a2, a0, 1
+; RV64-NEXT: sltu a0, a2, a0
+; RV64-NEXT: sd a2, 0(a1)
+; RV64-NEXT: ret
+;
+; RV32ZBA-LABEL: uaddo.i64.constant_one:
+; RV32ZBA: # %bb.0: # %entry
+; RV32ZBA-NEXT: mv a3, a0
+; RV32ZBA-NEXT: addi a4, a0, 1
+; RV32ZBA-NEXT: sltu a0, a4, a0
+; RV32ZBA-NEXT: add a5, a1, a0
+; RV32ZBA-NEXT: bgeu a4, a3, .LBB11_2
+; RV32ZBA-NEXT: # %bb.1: # %entry
+; RV32ZBA-NEXT: sltu a0, a5, a1
+; RV32ZBA-NEXT: .LBB11_2: # %entry
+; RV32ZBA-NEXT: sw a4, 0(a2)
+; RV32ZBA-NEXT: sw a5, 4(a2)
+; RV32ZBA-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_one:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 1
+; RV64ZBA-NEXT: sltu a0, a2, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+entry:
+ %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
; RV32-LABEL: ssubo1.i32:
; RV32: # %bb.0: # %entry
@@ -747,13 +835,13 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-NEXT: sub a3, a1, a3
; RV32-NEXT: sub a3, a3, a5
; RV32-NEXT: sub a2, a0, a2
-; RV32-NEXT: beq a3, a1, .LBB16_2
+; RV32-NEXT: beq a3, a1, .LBB18_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a1, a3
-; RV32-NEXT: j .LBB16_3
-; RV32-NEXT: .LBB16_2:
+; RV32-NEXT: j .LBB18_3
+; RV32-NEXT: .LBB18_2:
; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: .LBB16_3: # %entry
+; RV32-NEXT: .LBB18_3: # %entry
; RV32-NEXT: sw a2, 0(a4)
; RV32-NEXT: sw a3, 4(a4)
; RV32-NEXT: ret
@@ -771,13 +859,13 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32ZBA-NEXT: sub a3, a1, a3
; RV32ZBA-NEXT: sub a3, a3, a5
; RV32ZBA-NEXT: sub a2, a0, a2
-; RV32ZBA-NEXT: beq a3, a1, .LBB16_2
+; RV32ZBA-NEXT: beq a3, a1, .LBB18_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a1, a3
-; RV32ZBA-NEXT: j .LBB16_3
-; RV32ZBA-NEXT: .LBB16_2:
+; RV32ZBA-NEXT: j .LBB18_3
+; RV32ZBA-NEXT: .LBB18_2:
; RV32ZBA-NEXT: sltu a0, a0, a2
-; RV32ZBA-NEXT: .LBB16_3: # %entry
+; RV32ZBA-NEXT: .LBB18_3: # %entry
; RV32ZBA-NEXT: sw a2, 0(a4)
; RV32ZBA-NEXT: sw a3, 4(a4)
; RV32ZBA-NEXT: ret
@@ -1418,10 +1506,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: add a2, a0, a1
; RV32-NEXT: slt a2, a2, a0
; RV32-NEXT: slti a3, a1, 0
-; RV32-NEXT: bne a3, a2, .LBB26_2
+; RV32-NEXT: bne a3, a2, .LBB28_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB26_2: # %entry
+; RV32-NEXT: .LBB28_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: saddo.select.i32:
@@ -1430,10 +1518,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a3, a0
; RV64-NEXT: add a4, a3, a2
; RV64-NEXT: addw a2, a3, a2
-; RV64-NEXT: bne a2, a4, .LBB26_2
+; RV64-NEXT: bne a2, a4, .LBB28_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB26_2: # %entry
+; RV64-NEXT: .LBB28_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: saddo.select.i32:
@@ -1441,10 +1529,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: add a2, a0, a1
; RV32ZBA-NEXT: slt a2, a2, a0
; RV32ZBA-NEXT: slti a3, a1, 0
-; RV32ZBA-NEXT: bne a3, a2, .LBB26_2
+; RV32ZBA-NEXT: bne a3, a2, .LBB28_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB26_2: # %entry
+; RV32ZBA-NEXT: .LBB28_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: saddo.select.i32:
@@ -1453,10 +1541,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a3, a0
; RV64ZBA-NEXT: add a4, a3, a2
; RV64ZBA-NEXT: addw a2, a3, a2
-; RV64ZBA-NEXT: bne a2, a4, .LBB26_2
+; RV64ZBA-NEXT: bne a2, a4, .LBB28_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB26_2: # %entry
+; RV64ZBA-NEXT: .LBB28_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1521,11 +1609,11 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a5, a1, a3
; RV32-NEXT: not a5, a5
; RV32-NEXT: and a4, a5, a4
-; RV32-NEXT: bltz a4, .LBB28_2
+; RV32-NEXT: bltz a4, .LBB30_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB28_2: # %entry
+; RV32-NEXT: .LBB30_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: saddo.select.i64:
@@ -1533,10 +1621,10 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a2, a2, a0
; RV64-NEXT: slti a3, a1, 0
-; RV64-NEXT: bne a3, a2, .LBB28_2
+; RV64-NEXT: bne a3, a2, .LBB30_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB28_2: # %entry
+; RV64-NEXT: .LBB30_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: saddo.select.i64:
@@ -1549,11 +1637,11 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a5, a1, a3
; RV32ZBA-NEXT: not a5, a5
; RV32ZBA-NEXT: and a4, a5, a4
-; RV32ZBA-NEXT: bltz a4, .LBB28_2
+; RV32ZBA-NEXT: bltz a4, .LBB30_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
-; RV32ZBA-NEXT: .LBB28_2: # %entry
+; RV32ZBA-NEXT: .LBB30_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: saddo.select.i64:
@@ -1561,10 +1649,10 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: add a2, a0, a1
; RV64ZBA-NEXT: slt a2, a2, a0
; RV64ZBA-NEXT: slti a3, a1, 0
-; RV64ZBA-NEXT: bne a3, a2, .LBB28_2
+; RV64ZBA-NEXT: bne a3, a2, .LBB30_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB28_2: # %entry
+; RV64ZBA-NEXT: .LBB30_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1630,39 +1718,39 @@ define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: uaddo.select.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: add a2, a0, a1
-; RV32-NEXT: bltu a2, a0, .LBB30_2
+; RV32-NEXT: bltu a2, a0, .LBB32_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB30_2: # %entry
+; RV32-NEXT: .LBB32_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: uaddo.select.i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addw a2, a0, a1
; RV64-NEXT: sext.w a3, a0
-; RV64-NEXT: bltu a2, a3, .LBB30_2
+; RV64-NEXT: bltu a2, a3, .LBB32_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB30_2: # %entry
+; RV64-NEXT: .LBB32_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: uaddo.select.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: add a2, a0, a1
-; RV32ZBA-NEXT: bltu a2, a0, .LBB30_2
+; RV32ZBA-NEXT: bltu a2, a0, .LBB32_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB30_2: # %entry
+; RV32ZBA-NEXT: .LBB32_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: uaddo.select.i32:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addw a2, a0, a1
; RV64ZBA-NEXT: sext.w a3, a0
-; RV64ZBA-NEXT: bltu a2, a3, .LBB30_2
+; RV64ZBA-NEXT: bltu a2, a3, .LBB32_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB30_2: # %entry
+; RV64ZBA-NEXT: .LBB32_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1715,15 +1803,15 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: add a4, a0, a2
; RV32-NEXT: sltu a4, a4, a0
; RV32-NEXT: add a5, a5, a4
-; RV32-NEXT: bne a5, a1, .LBB32_3
+; RV32-NEXT: bne a5, a1, .LBB34_3
; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: beqz a4, .LBB32_4
-; RV32-NEXT: .LBB32_2: # %entry
+; RV32-NEXT: beqz a4, .LBB34_4
+; RV32-NEXT: .LBB34_2: # %entry
; RV32-NEXT: ret
-; RV32-NEXT: .LBB32_3: # %entry
+; RV32-NEXT: .LBB34_3: # %entry
; RV32-NEXT: sltu a4, a5, a1
-; RV32-NEXT: bnez a4, .LBB32_2
-; RV32-NEXT: .LBB32_4: # %entry
+; RV32-NEXT: bnez a4, .LBB34_2
+; RV32-NEXT: .LBB34_4: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
; RV32-NEXT: ret
@@ -1731,10 +1819,10 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV64-LABEL: uaddo.select.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: add a2, a0, a1
-; RV64-NEXT: bltu a2, a0, .LBB32_2
+; RV64-NEXT: bltu a2, a0, .LBB34_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB32_2: # %entry
+; RV64-NEXT: .LBB34_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: uaddo.select.i64:
@@ -1743,15 +1831,15 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: add a4, a0, a2
; RV32ZBA-NEXT: sltu a4, a4, a0
; RV32ZBA-NEXT: add a5, a5, a4
-; RV32ZBA-NEXT: bne a5, a1, .LBB32_3
+; RV32ZBA-NEXT: bne a5, a1, .LBB34_3
; RV32ZBA-NEXT: # %bb.1: # %entry
-; RV32ZBA-NEXT: beqz a4, .LBB32_4
-; RV32ZBA-NEXT: .LBB32_2: # %entry
+; RV32ZBA-NEXT: beqz a4, .LBB34_4
+; RV32ZBA-NEXT: .LBB34_2: # %entry
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB32_3: # %entry
+; RV32ZBA-NEXT: .LBB34_3: # %entry
; RV32ZBA-NEXT: sltu a4, a5, a1
-; RV32ZBA-NEXT: bnez a4, .LBB32_2
-; RV32ZBA-NEXT: .LBB32_4: # %entry
+; RV32ZBA-NEXT: bnez a4, .LBB34_2
+; RV32ZBA-NEXT: .LBB34_4: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
; RV32ZBA-NEXT: ret
@@ -1759,10 +1847,10 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV64ZBA-LABEL: uaddo.select.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: add a2, a0, a1
-; RV64ZBA-NEXT: bltu a2, a0, .LBB32_2
+; RV64ZBA-NEXT: bltu a2, a0, .LBB34_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB32_2: # %entry
+; RV64ZBA-NEXT: .LBB34_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1778,10 +1866,10 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a2, a3, a0
-; RV32-NEXT: beq a2, a1, .LBB33_2
+; RV32-NEXT: beq a2, a1, .LBB35_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a2, a1
-; RV32-NEXT: .LBB33_2: # %entry
+; RV32-NEXT: .LBB35_2: # %entry
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: ret
;
@@ -1798,10 +1886,10 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: add a2, a0, a2
; RV32ZBA-NEXT: sltu a0, a2, a0
; RV32ZBA-NEXT: add a2, a3, a0
-; RV32ZBA-NEXT: beq a2, a1, .LBB33_2
+; RV32ZBA-NEXT: beq a2, a1, .LBB35_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a2, a1
-; RV32ZBA-NEXT: .LBB33_2: # %entry
+; RV32ZBA-NEXT: .LBB35_2: # %entry
; RV32ZBA-NEXT: xori a0, a0, 1
; RV32ZBA-NEXT: ret
;
@@ -1824,10 +1912,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: sgtz a2, a1
; RV32-NEXT: sub a3, a0, a1
; RV32-NEXT: slt a3, a3, a0
-; RV32-NEXT: bne a2, a3, .LBB34_2
+; RV32-NEXT: bne a2, a3, .LBB36_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB34_2: # %entry
+; RV32-NEXT: .LBB36_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: ssubo.select.i32:
@@ -1836,10 +1924,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a3, a0
; RV64-NEXT: sub a4, a3, a2
; RV64-NEXT: subw a2, a3, a2
-; RV64-NEXT: bne a2, a4, .LBB34_2
+; RV64-NEXT: bne a2, a4, .LBB36_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB34_2: # %entry
+; RV64-NEXT: .LBB36_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: ssubo.select.i32:
@@ -1847,10 +1935,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: sgtz a2, a1
; RV32ZBA-NEXT: sub a3, a0, a1
; RV32ZBA-NEXT: slt a3, a3, a0
-; RV32ZBA-NEXT: bne a2, a3, .LBB34_2
+; RV32ZBA-NEXT: bne a2, a3, .LBB36_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB34_2: # %entry
+; RV32ZBA-NEXT: .LBB36_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: ssubo.select.i32:
@@ -1859,10 +1947,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a3, a0
; RV64ZBA-NEXT: sub a4, a3, a2
; RV64ZBA-NEXT: subw a2, a3, a2
-; RV64ZBA-NEXT: bne a2, a4, .LBB34_2
+; RV64ZBA-NEXT: bne a2, a4, .LBB36_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB34_2: # %entry
+; RV64ZBA-NEXT: .LBB36_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1925,11 +2013,11 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a4, a1, a4
; RV32-NEXT: xor a5, a1, a3
; RV32-NEXT: and a4, a5, a4
-; RV32-NEXT: bltz a4, .LBB36_2
+; RV32-NEXT: bltz a4, .LBB38_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB36_2: # %entry
+; RV32-NEXT: .LBB38_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: ssubo.select.i64:
@@ -1937,10 +2025,10 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a3, a0, a1
; RV64-NEXT: slt a3, a3, a0
-; RV64-NEXT: bne a2, a3, .LBB36_2
+; RV64-NEXT: bne a2, a3, .LBB38_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB36_2: # %entry
+; RV64-NEXT: .LBB38_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: ssubo.select.i64:
@@ -1951,11 +2039,11 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a4, a1, a4
; RV32ZBA-NEXT: xor a5, a1, a3
; RV32ZBA-NEXT: and a4, a5, a4
-; RV32ZBA-NEXT: bltz a4, .LBB36_2
+; RV32ZBA-NEXT: bltz a4, .LBB38_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
-; RV32ZBA-NEXT: .LBB36_2: # %entry
+; RV32ZBA-NEXT: .LBB38_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: ssubo.select.i64:
@@ -1963,10 +2051,10 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: sgtz a2, a1
; RV64ZBA-NEXT: sub a3, a0, a1
; RV64ZBA-NEXT: slt a3, a3, a0
-; RV64ZBA-NEXT: bne a2, a3, .LBB36_2
+; RV64ZBA-NEXT: bne a2, a3, .LBB38_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB36_2: # %entry
+; RV64ZBA-NEXT: .LBB38_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2028,39 +2116,39 @@ define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: usubo.select.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: sub a2, a0, a1
-; RV32-NEXT: bltu a0, a2, .LBB38_2
+; RV32-NEXT: bltu a0, a2, .LBB40_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB38_2: # %entry
+; RV32-NEXT: .LBB40_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: usubo.select.i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: subw a2, a0, a1
; RV64-NEXT: sext.w a3, a0
-; RV64-NEXT: bltu a3, a2, .LBB38_2
+; RV64-NEXT: bltu a3, a2, .LBB40_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB38_2: # %entry
+; RV64-NEXT: .LBB40_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.select.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: sub a2, a0, a1
-; RV32ZBA-NEXT: bltu a0, a2, .LBB38_2
+; RV32ZBA-NEXT: bltu a0, a2, .LBB40_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB38_2: # %entry
+; RV32ZBA-NEXT: .LBB40_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: usubo.select.i32:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: subw a2, a0, a1
; RV64ZBA-NEXT: sext.w a3, a0
-; RV64ZBA-NEXT: bltu a3, a2, .LBB38_2
+; RV64ZBA-NEXT: bltu a3, a2, .LBB40_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB38_2: # %entry
+; RV64ZBA-NEXT: .LBB40_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -2112,28 +2200,28 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: sltu a4, a0, a2
; RV32-NEXT: sub a5, a1, a3
; RV32-NEXT: sub a4, a5, a4
-; RV32-NEXT: beq a4, a1, .LBB40_2
+; RV32-NEXT: beq a4, a1, .LBB42_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a4
-; RV32-NEXT: beqz a4, .LBB40_3
-; RV32-NEXT: j .LBB40_4
-; RV32-NEXT: .LBB40_2:
+; RV32-NEXT: beqz a4, .LBB42_3
+; RV32-NEXT: j .LBB42_4
+; RV32-NEXT: .LBB42_2:
; RV32-NEXT: sub a4, a0, a2
; RV32-NEXT: sltu a4, a0, a4
-; RV32-NEXT: bnez a4, .LBB40_4
-; RV32-NEXT: .LBB40_3: # %entry
+; RV32-NEXT: bnez a4, .LBB42_4
+; RV32-NEXT: .LBB42_3: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB40_4: # %entry
+; RV32-NEXT: .LBB42_4: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: usubo.select.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: sub a2, a0, a1
-; RV64-NEXT: bltu a0, a2, .LBB40_2
+; RV64-NEXT: bltu a0, a2, .LBB42_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB40_2: # %entry
+; RV64-NEXT: .LBB42_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.select.i64:
@@ -2141,28 +2229,28 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: sltu a4, a0, a2
; RV32ZBA-NEXT: sub a5, a1, a3
; RV32ZBA-NEXT: sub a4, a5, a4
-; RV32ZBA-NEXT: beq a4, a1, .LBB40_2
+; RV32ZBA-NEXT: beq a4, a1, .LBB42_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a4, a1, a4
-; RV32ZBA-NEXT: beqz a4, .LBB40_3
-; RV32ZBA-NEXT: j .LBB40_4
-; RV32ZBA-NEXT: .LBB40_2:
+; RV32ZBA-NEXT: beqz a4, .LBB42_3
+; RV32ZBA-NEXT: j .LBB42_4
+; RV32ZBA-NEXT: .LBB42_2:
; RV32ZBA-NEXT: sub a4, a0, a2
; RV32ZBA-NEXT: sltu a4, a0, a4
-; RV32ZBA-NEXT: bnez a4, .LBB40_4
-; RV32ZBA-NEXT: .LBB40_3: # %entry
+; RV32ZBA-NEXT: bnez a4, .LBB42_4
+; RV32ZBA-NEXT: .LBB42_3: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
-; RV32ZBA-NEXT: .LBB40_4: # %entry
+; RV32ZBA-NEXT: .LBB42_4: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: usubo.select.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: sub a2, a0, a1
-; RV64ZBA-NEXT: bltu a0, a2, .LBB40_2
+; RV64ZBA-NEXT: bltu a0, a2, .LBB42_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB40_2: # %entry
+; RV64ZBA-NEXT: .LBB42_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2177,12 +2265,12 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: sltu a4, a0, a2
; RV32-NEXT: sub a3, a1, a3
; RV32-NEXT: sub a3, a3, a4
-; RV32-NEXT: beq a3, a1, .LBB41_2
+; RV32-NEXT: beq a3, a1, .LBB43_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a1, a3
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: ret
-; RV32-NEXT: .LBB41_2:
+; RV32-NEXT: .LBB43_2:
; RV32-NEXT: sub a1, a0, a2
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: xori a0, a0, 1
@@ -2200,12 +2288,12 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: sltu a4, a0, a2
; RV32ZBA-NEXT: sub a3, a1, a3
; RV32ZBA-NEXT: sub a3, a3, a4
-; RV32ZBA-NEXT: beq a3, a1, .LBB41_2
+; RV32ZBA-NEXT: beq a3, a1, .LBB43_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a1, a3
; RV32ZBA-NEXT: xori a0, a0, 1
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB41_2:
+; RV32ZBA-NEXT: .LBB43_2:
; RV32ZBA-NEXT: sub a1, a0, a2
; RV32ZBA-NEXT: sltu a0, a0, a1
; RV32ZBA-NEXT: xori a0, a0, 1
@@ -2230,10 +2318,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: mulh a2, a0, a1
; RV32-NEXT: mul a3, a0, a1
; RV32-NEXT: srai a3, a3, 31
-; RV32-NEXT: bne a2, a3, .LBB42_2
+; RV32-NEXT: bne a2, a3, .LBB44_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB42_2: # %entry
+; RV32-NEXT: .LBB44_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: smulo.select.i32:
@@ -2242,10 +2330,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a3, a0
; RV64-NEXT: mul a4, a3, a2
; RV64-NEXT: mulw a2, a3, a2
-; RV64-NEXT: bne a2, a4, .LBB42_2
+; RV64-NEXT: bne a2, a4, .LBB44_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB42_2: # %entry
+; RV64-NEXT: .LBB44_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: smulo.select.i32:
@@ -2253,10 +2341,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: mulh a2, a0, a1
; RV32ZBA-NEXT: mul a3, a0, a1
; RV32ZBA-NEXT: srai a3, a3, 31
-; RV32ZBA-NEXT: bne a2, a3, .LBB42_2
+; RV32ZBA-NEXT: bne a2, a3, .LBB44_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB42_2: # %entry
+; RV32ZBA-NEXT: .LBB44_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: smulo.select.i32:
@@ -2265,10 +2353,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a3, a0
; RV64ZBA-NEXT: mul a4, a3, a2
; RV64ZBA-NEXT: mulw a2, a3, a2
-; RV64ZBA-NEXT: bne a2, a4, .LBB42_2
+; RV64ZBA-NEXT: bne a2, a4, .LBB44_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB42_2: # %entry
+; RV64ZBA-NEXT: .LBB44_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -2372,11 +2460,11 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a5, a5, a4
; RV32-NEXT: xor a4, t6, a4
; RV32-NEXT: or a4, a4, a5
-; RV32-NEXT: bnez a4, .LBB44_2
+; RV32-NEXT: bnez a4, .LBB46_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB44_2: # %entry
+; RV32-NEXT: .LBB46_2: # %entry
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
@@ -2386,10 +2474,10 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a3, a0, a1
; RV64-NEXT: srai a3, a3, 63
-; RV64-NEXT: bne a2, a3, .LBB44_2
+; RV64-NEXT: bne a2, a3, .LBB46_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB44_2: # %entry
+; RV64-NEXT: .LBB46_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: smulo.select.i64:
@@ -2441,11 +2529,11 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a5, a5, a4
; RV32ZBA-NEXT: xor a4, t6, a4
; RV32ZBA-NEXT: or a4, a4, a5
-; RV32ZBA-NEXT: bnez a4, .LBB44_2
+; RV32ZBA-NEXT: bnez a4, .LBB46_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
-; RV32ZBA-NEXT: .LBB44_2: # %entry
+; RV32ZBA-NEXT: .LBB46_2: # %entry
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret
@@ -2455,10 +2543,10 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a3, a0, a1
; RV64ZBA-NEXT: srai a3, a3, 63
-; RV64ZBA-NEXT: bne a2, a3, .LBB44_2
+; RV64ZBA-NEXT: bne a2, a3, .LBB46_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB44_2: # %entry
+; RV64ZBA-NEXT: .LBB46_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2604,10 +2692,10 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: umulo.select.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: mulhu a2, a0, a1
-; RV32-NEXT: bnez a2, .LBB46_2
+; RV32-NEXT: bnez a2, .LBB48_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a1
-; RV32-NEXT: .LBB46_2: # %entry
+; RV32-NEXT: .LBB48_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: umulo.select.i32:
@@ -2616,19 +2704,19 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: mulhu a2, a3, a2
; RV64-NEXT: srli a2, a2, 32
-; RV64-NEXT: bnez a2, .LBB46_2
+; RV64-NEXT: bnez a2, .LBB48_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB46_2: # %entry
+; RV64-NEXT: .LBB48_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: umulo.select.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mulhu a2, a0, a1
-; RV32ZBA-NEXT: bnez a2, .LBB46_2
+; RV32ZBA-NEXT: bnez a2, .LBB48_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a1
-; RV32ZBA-NEXT: .LBB46_2: # %entry
+; RV32ZBA-NEXT: .LBB48_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: umulo.select.i32:
@@ -2637,10 +2725,10 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: zext.w a3, a0
; RV64ZBA-NEXT: mul a2, a3, a2
; RV64ZBA-NEXT: srli a2, a2, 32
-; RV64ZBA-NEXT: bnez a2, .LBB46_2
+; RV64ZBA-NEXT: bnez a2, .LBB48_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB46_2: # %entry
+; RV64ZBA-NEXT: .LBB48_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -2705,20 +2793,20 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: snez a6, a6
; RV32-NEXT: or a5, a5, a6
; RV32-NEXT: or a4, a5, a4
-; RV32-NEXT: bnez a4, .LBB48_2
+; RV32-NEXT: bnez a4, .LBB50_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3
-; RV32-NEXT: .LBB48_2: # %entry
+; RV32-NEXT: .LBB50_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: umulo.select.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a2, a0, a1
-; RV64-NEXT: bnez a2, .LBB48_2
+; RV64-NEXT: bnez a2, .LBB50_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: .LBB48_2: # %entry
+; RV64-NEXT: .LBB50_2: # %entry
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: umulo.select.i64:
@@ -2739,20 +2827,20 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: snez a6, a6
; RV32ZBA-NEXT: or a5, a5, a6
; RV32ZBA-NEXT: or a4, a5, a4
-; RV32ZBA-NEXT: bnez a4, .LBB48_2
+; RV32ZBA-NEXT: bnez a4, .LBB50_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3
-; RV32ZBA-NEXT: .LBB48_2: # %entry
+; RV32ZBA-NEXT: .LBB50_2: # %entry
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: umulo.select.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulhu a2, a0, a1
-; RV64ZBA-NEXT: bnez a2, .LBB48_2
+; RV64ZBA-NEXT: bnez a2, .LBB50_2
; RV64ZBA-NEXT: # %bb.1: # %entry
; RV64ZBA-NEXT: mv a0, a1
-; RV64ZBA-NEXT: .LBB48_2: # %entry
+; RV64ZBA-NEXT: .LBB50_2: # %entry
; RV64ZBA-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2832,11 +2920,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: add a2, a0, a1
; RV32-NEXT: slt a0, a2, a0
; RV32-NEXT: slti a1, a1, 0
-; RV32-NEXT: beq a1, a0, .LBB50_2
+; RV32-NEXT: beq a1, a0, .LBB52_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB50_2: # %continue
+; RV32-NEXT: .LBB52_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -2846,11 +2934,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: addw a0, a0, a1
-; RV64-NEXT: beq a0, a2, .LBB50_2
+; RV64-NEXT: beq a0, a2, .LBB52_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB50_2: # %continue
+; RV64-NEXT: .LBB52_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -2859,11 +2947,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: add a2, a0, a1
; RV32ZBA-NEXT: slt a0, a2, a0
; RV32ZBA-NEXT: slti a1, a1, 0
-; RV32ZBA-NEXT: beq a1, a0, .LBB50_2
+; RV32ZBA-NEXT: beq a1, a0, .LBB52_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB50_2: # %continue
+; RV32ZBA-NEXT: .LBB52_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -2873,11 +2961,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a0, a0
; RV64ZBA-NEXT: add a2, a0, a1
; RV64ZBA-NEXT: addw a0, a0, a1
-; RV64ZBA-NEXT: beq a0, a2, .LBB50_2
+; RV64ZBA-NEXT: beq a0, a2, .LBB52_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB50_2: # %continue
+; RV64ZBA-NEXT: .LBB52_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -2904,11 +2992,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: not a1, a1
; RV32-NEXT: and a0, a1, a0
-; RV32-NEXT: bgez a0, .LBB51_2
+; RV32-NEXT: bgez a0, .LBB53_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB51_2: # %continue
+; RV32-NEXT: .LBB53_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -2917,11 +3005,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: slti a1, a1, 0
-; RV64-NEXT: beq a1, a0, .LBB51_2
+; RV64-NEXT: beq a1, a0, .LBB53_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB51_2: # %continue
+; RV64-NEXT: .LBB53_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -2935,11 +3023,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a1, a1, a3
; RV32ZBA-NEXT: not a1, a1
; RV32ZBA-NEXT: and a0, a1, a0
-; RV32ZBA-NEXT: bgez a0, .LBB51_2
+; RV32ZBA-NEXT: bgez a0, .LBB53_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB51_2: # %continue
+; RV32ZBA-NEXT: .LBB53_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -2948,11 +3036,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: add a2, a0, a1
; RV64ZBA-NEXT: slt a0, a2, a0
; RV64ZBA-NEXT: slti a1, a1, 0
-; RV64ZBA-NEXT: beq a1, a0, .LBB51_2
+; RV64ZBA-NEXT: beq a1, a0, .LBB53_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB51_2: # %continue
+; RV64ZBA-NEXT: .LBB53_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -2972,11 +3060,11 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: uaddo.br.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: bgeu a1, a0, .LBB52_2
+; RV32-NEXT: bgeu a1, a0, .LBB54_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB52_2: # %continue
+; RV32-NEXT: .LBB54_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -2984,22 +3072,22 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addw a1, a0, a1
; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: bgeu a1, a0, .LBB52_2
+; RV64-NEXT: bgeu a1, a0, .LBB54_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB52_2: # %continue
+; RV64-NEXT: .LBB54_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: uaddo.br.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: add a1, a0, a1
-; RV32ZBA-NEXT: bgeu a1, a0, .LBB52_2
+; RV32ZBA-NEXT: bgeu a1, a0, .LBB54_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB52_2: # %continue
+; RV32ZBA-NEXT: .LBB54_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3007,11 +3095,11 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addw a1, a0, a1
; RV64ZBA-NEXT: sext.w a0, a0
-; RV64ZBA-NEXT: bgeu a1, a0, .LBB52_2
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB54_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB52_2: # %continue
+; RV64ZBA-NEXT: .LBB54_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3034,26 +3122,26 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a2, a3, a0
-; RV32-NEXT: beq a2, a1, .LBB53_2
+; RV32-NEXT: beq a2, a1, .LBB55_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a2, a1
-; RV32-NEXT: .LBB53_2: # %entry
-; RV32-NEXT: beqz a0, .LBB53_4
+; RV32-NEXT: .LBB55_2: # %entry
+; RV32-NEXT: beqz a0, .LBB55_4
; RV32-NEXT: # %bb.3: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB53_4: # %continue
+; RV32-NEXT: .LBB55_4: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
; RV64-LABEL: uaddo.br.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: bgeu a1, a0, .LBB53_2
+; RV64-NEXT: bgeu a1, a0, .LBB55_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB53_2: # %continue
+; RV64-NEXT: .LBB55_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3063,26 +3151,26 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: add a2, a0, a2
; RV32ZBA-NEXT: sltu a0, a2, a0
; RV32ZBA-NEXT: add a2, a3, a0
-; RV32ZBA-NEXT: beq a2, a1, .LBB53_2
+; RV32ZBA-NEXT: beq a2, a1, .LBB55_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a2, a1
-; RV32ZBA-NEXT: .LBB53_2: # %entry
-; RV32ZBA-NEXT: beqz a0, .LBB53_4
+; RV32ZBA-NEXT: .LBB55_2: # %entry
+; RV32ZBA-NEXT: beqz a0, .LBB55_4
; RV32ZBA-NEXT: # %bb.3: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB53_4: # %continue
+; RV32ZBA-NEXT: .LBB55_4: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: uaddo.br.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: add a1, a0, a1
-; RV64ZBA-NEXT: bgeu a1, a0, .LBB53_2
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB55_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB53_2: # %continue
+; RV64ZBA-NEXT: .LBB55_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3104,11 +3192,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: sgtz a2, a1
; RV32-NEXT: sub a1, a0, a1
; RV32-NEXT: slt a0, a1, a0
-; RV32-NEXT: beq a2, a0, .LBB54_2
+; RV32-NEXT: beq a2, a0, .LBB56_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB54_2: # %continue
+; RV32-NEXT: .LBB56_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3118,11 +3206,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: sub a2, a0, a1
; RV64-NEXT: subw a0, a0, a1
-; RV64-NEXT: beq a0, a2, .LBB54_2
+; RV64-NEXT: beq a0, a2, .LBB56_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB54_2: # %continue
+; RV64-NEXT: .LBB56_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3131,11 +3219,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: sgtz a2, a1
; RV32ZBA-NEXT: sub a1, a0, a1
; RV32ZBA-NEXT: slt a0, a1, a0
-; RV32ZBA-NEXT: beq a2, a0, .LBB54_2
+; RV32ZBA-NEXT: beq a2, a0, .LBB56_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB54_2: # %continue
+; RV32ZBA-NEXT: .LBB56_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3145,11 +3233,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a0, a0
; RV64ZBA-NEXT: sub a2, a0, a1
; RV64ZBA-NEXT: subw a0, a0, a1
-; RV64ZBA-NEXT: beq a0, a2, .LBB54_2
+; RV64ZBA-NEXT: beq a0, a2, .LBB56_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB54_2: # %continue
+; RV64ZBA-NEXT: .LBB56_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3174,11 +3262,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: and a0, a1, a0
-; RV32-NEXT: bgez a0, .LBB55_2
+; RV32-NEXT: bgez a0, .LBB57_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB55_2: # %continue
+; RV32-NEXT: .LBB57_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3187,11 +3275,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0
-; RV64-NEXT: beq a2, a0, .LBB55_2
+; RV64-NEXT: beq a2, a0, .LBB57_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB55_2: # %continue
+; RV64-NEXT: .LBB57_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3203,11 +3291,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a0, a1, a0
; RV32ZBA-NEXT: xor a1, a1, a3
; RV32ZBA-NEXT: and a0, a1, a0
-; RV32ZBA-NEXT: bgez a0, .LBB55_2
+; RV32ZBA-NEXT: bgez a0, .LBB57_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB55_2: # %continue
+; RV32ZBA-NEXT: .LBB57_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3216,11 +3304,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: sgtz a2, a1
; RV64ZBA-NEXT: sub a1, a0, a1
; RV64ZBA-NEXT: slt a0, a1, a0
-; RV64ZBA-NEXT: beq a2, a0, .LBB55_2
+; RV64ZBA-NEXT: beq a2, a0, .LBB57_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB55_2: # %continue
+; RV64ZBA-NEXT: .LBB57_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3240,11 +3328,11 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: usubo.br.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: sub a1, a0, a1
-; RV32-NEXT: bgeu a0, a1, .LBB56_2
+; RV32-NEXT: bgeu a0, a1, .LBB58_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB56_2: # %continue
+; RV32-NEXT: .LBB58_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3252,22 +3340,22 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: subw a1, a0, a1
; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: bgeu a0, a1, .LBB56_2
+; RV64-NEXT: bgeu a0, a1, .LBB58_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB56_2: # %continue
+; RV64-NEXT: .LBB58_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.br.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: sub a1, a0, a1
-; RV32ZBA-NEXT: bgeu a0, a1, .LBB56_2
+; RV32ZBA-NEXT: bgeu a0, a1, .LBB58_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB56_2: # %continue
+; RV32ZBA-NEXT: .LBB58_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3275,11 +3363,11 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: subw a1, a0, a1
; RV64ZBA-NEXT: sext.w a0, a0
-; RV64ZBA-NEXT: bgeu a0, a1, .LBB56_2
+; RV64ZBA-NEXT: bgeu a0, a1, .LBB58_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB56_2: # %continue
+; RV64ZBA-NEXT: .LBB58_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3301,29 +3389,29 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: sltu a4, a0, a2
; RV32-NEXT: sub a3, a1, a3
; RV32-NEXT: sub a3, a3, a4
-; RV32-NEXT: beq a3, a1, .LBB57_3
+; RV32-NEXT: beq a3, a1, .LBB59_3
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a1, a3
-; RV32-NEXT: bnez a0, .LBB57_4
-; RV32-NEXT: .LBB57_2: # %continue
+; RV32-NEXT: bnez a0, .LBB59_4
+; RV32-NEXT: .LBB59_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
-; RV32-NEXT: .LBB57_3:
+; RV32-NEXT: .LBB59_3:
; RV32-NEXT: sub a1, a0, a2
; RV32-NEXT: sltu a0, a0, a1
-; RV32-NEXT: beqz a0, .LBB57_2
-; RV32-NEXT: .LBB57_4: # %overflow
+; RV32-NEXT: beqz a0, .LBB59_2
+; RV32-NEXT: .LBB59_4: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
;
; RV64-LABEL: usubo.br.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: sub a1, a0, a1
-; RV64-NEXT: bgeu a0, a1, .LBB57_2
+; RV64-NEXT: bgeu a0, a1, .LBB59_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB57_2: # %continue
+; RV64-NEXT: .LBB59_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3332,29 +3420,29 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: sltu a4, a0, a2
; RV32ZBA-NEXT: sub a3, a1, a3
; RV32ZBA-NEXT: sub a3, a3, a4
-; RV32ZBA-NEXT: beq a3, a1, .LBB57_3
+; RV32ZBA-NEXT: beq a3, a1, .LBB59_3
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a1, a3
-; RV32ZBA-NEXT: bnez a0, .LBB57_4
-; RV32ZBA-NEXT: .LBB57_2: # %continue
+; RV32ZBA-NEXT: bnez a0, .LBB59_4
+; RV32ZBA-NEXT: .LBB59_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB57_3:
+; RV32ZBA-NEXT: .LBB59_3:
; RV32ZBA-NEXT: sub a1, a0, a2
; RV32ZBA-NEXT: sltu a0, a0, a1
-; RV32ZBA-NEXT: beqz a0, .LBB57_2
-; RV32ZBA-NEXT: .LBB57_4: # %overflow
+; RV32ZBA-NEXT: beqz a0, .LBB59_2
+; RV32ZBA-NEXT: .LBB59_4: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: usubo.br.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: sub a1, a0, a1
-; RV64ZBA-NEXT: bgeu a0, a1, .LBB57_2
+; RV64ZBA-NEXT: bgeu a0, a1, .LBB59_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB57_2: # %continue
+; RV64ZBA-NEXT: .LBB59_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3376,11 +3464,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
; RV32-NEXT: mulh a2, a0, a1
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: beq a2, a0, .LBB58_2
+; RV32-NEXT: beq a2, a0, .LBB60_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB58_2: # %continue
+; RV32-NEXT: .LBB60_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3390,11 +3478,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: mul a2, a0, a1
; RV64-NEXT: mulw a0, a0, a1
-; RV64-NEXT: beq a0, a2, .LBB58_2
+; RV64-NEXT: beq a0, a2, .LBB60_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB58_2: # %continue
+; RV64-NEXT: .LBB60_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3403,11 +3491,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
; RV32ZBA-NEXT: mulh a2, a0, a1
; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: srai a0, a0, 31
-; RV32ZBA-NEXT: beq a2, a0, .LBB58_2
+; RV32ZBA-NEXT: beq a2, a0, .LBB60_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB58_2: # %continue
+; RV32ZBA-NEXT: .LBB60_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3417,11 +3505,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: sext.w a0, a0
; RV64ZBA-NEXT: mul a2, a0, a1
; RV64ZBA-NEXT: mulw a0, a0, a1
-; RV64ZBA-NEXT: beq a0, a2, .LBB58_2
+; RV64ZBA-NEXT: beq a0, a2, .LBB60_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB58_2: # %continue
+; RV64ZBA-NEXT: .LBB60_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3487,13 +3575,13 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a1, t6, a1
; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: beqz a0, .LBB59_2
+; RV32-NEXT: beqz a0, .LBB61_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
-; RV32-NEXT: j .LBB59_3
-; RV32-NEXT: .LBB59_2: # %continue
+; RV32-NEXT: j .LBB61_3
+; RV32-NEXT: .LBB61_2: # %continue
; RV32-NEXT: li a0, 1
-; RV32-NEXT: .LBB59_3: # %overflow
+; RV32-NEXT: .LBB61_3: # %overflow
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
@@ -3503,11 +3591,11 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: beq a2, a0, .LBB59_2
+; RV64-NEXT: beq a2, a0, .LBB61_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB59_2: # %continue
+; RV64-NEXT: .LBB61_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3560,13 +3648,13 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: xor a0, a0, a1
; RV32ZBA-NEXT: xor a1, t6, a1
; RV32ZBA-NEXT: or a0, a1, a0
-; RV32ZBA-NEXT: beqz a0, .LBB59_2
+; RV32ZBA-NEXT: beqz a0, .LBB61_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
-; RV32ZBA-NEXT: j .LBB59_3
-; RV32ZBA-NEXT: .LBB59_2: # %continue
+; RV32ZBA-NEXT: j .LBB61_3
+; RV32ZBA-NEXT: .LBB61_2: # %continue
; RV32ZBA-NEXT: li a0, 1
-; RV32ZBA-NEXT: .LBB59_3: # %overflow
+; RV32ZBA-NEXT: .LBB61_3: # %overflow
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret
@@ -3576,11 +3664,11 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 63
-; RV64ZBA-NEXT: beq a2, a0, .LBB59_2
+; RV64ZBA-NEXT: beq a2, a0, .LBB61_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB59_2: # %continue
+; RV64ZBA-NEXT: .LBB61_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3637,11 +3725,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a1, t4, a1
; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: beqz a0, .LBB60_2
+; RV32-NEXT: beqz a0, .LBB62_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB60_2: # %continue
+; RV32-NEXT: .LBB62_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3651,11 +3739,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: beq a2, a0, .LBB60_2
+; RV64-NEXT: beq a2, a0, .LBB62_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB60_2: # %continue
+; RV64-NEXT: .LBB62_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3699,11 +3787,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV32ZBA-NEXT: xor a0, a0, a1
; RV32ZBA-NEXT: xor a1, t4, a1
; RV32ZBA-NEXT: or a0, a1, a0
-; RV32ZBA-NEXT: beqz a0, .LBB60_2
+; RV32ZBA-NEXT: beqz a0, .LBB62_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB60_2: # %continue
+; RV32ZBA-NEXT: .LBB62_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3713,11 +3801,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 63
-; RV64ZBA-NEXT: beq a2, a0, .LBB60_2
+; RV64ZBA-NEXT: beq a2, a0, .LBB62_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB60_2: # %continue
+; RV64ZBA-NEXT: .LBB62_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3737,11 +3825,11 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
; RV32-LABEL: umulo.br.i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: mulhu a0, a0, a1
-; RV32-NEXT: beqz a0, .LBB61_2
+; RV32-NEXT: beqz a0, .LBB63_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB61_2: # %continue
+; RV32-NEXT: .LBB63_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
@@ -3751,22 +3839,22 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: mulhu a0, a0, a1
; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: beqz a0, .LBB61_2
+; RV64-NEXT: beqz a0, .LBB63_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB61_2: # %continue
+; RV64-NEXT: .LBB63_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: umulo.br.i32:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mulhu a0, a0, a1
-; RV32ZBA-NEXT: beqz a0, .LBB61_2
+; RV32ZBA-NEXT: beqz a0, .LBB63_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB61_2: # %continue
+; RV32ZBA-NEXT: .LBB63_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
@@ -3776,11 +3864,11 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srli a0, a0, 32
-; RV64ZBA-NEXT: beqz a0, .LBB61_2
+; RV64ZBA-NEXT: beqz a0, .LBB63_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB61_2: # %continue
+; RV64ZBA-NEXT: .LBB63_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3815,22 +3903,22 @@ define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
; RV32-NEXT: snez a0, a0
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: or a0, a0, a4
-; RV32-NEXT: beqz a0, .LBB62_2
+; RV32-NEXT: beqz a0, .LBB64_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB62_2: # %continue
+; RV32-NEXT: .LBB64_2: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
; RV64-LABEL: umulo.br.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a0, a0, a1
-; RV64-NEXT: beqz a0, .LBB62_2
+; RV64-NEXT: beqz a0, .LBB64_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB62_2: # %continue
+; RV64-NEXT: .LBB64_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3852,22 +3940,22 @@ define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
; RV32ZBA-NEXT: snez a0, a0
; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: or a0, a0, a4
-; RV32ZBA-NEXT: beqz a0, .LBB62_2
+; RV32ZBA-NEXT: beqz a0, .LBB64_2
; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB62_2: # %continue
+; RV32ZBA-NEXT: .LBB64_2: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: umulo.br.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulhu a0, a0, a1
-; RV64ZBA-NEXT: beqz a0, .LBB62_2
+; RV64ZBA-NEXT: beqz a0, .LBB64_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB62_2: # %continue
+; RV64ZBA-NEXT: .LBB64_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
@@ -3890,26 +3978,26 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a2, a1, a1
; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: beq a2, a1, .LBB63_2
+; RV32-NEXT: beq a2, a1, .LBB65_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a0, a2, a1
-; RV32-NEXT: .LBB63_2: # %entry
-; RV32-NEXT: beqz a0, .LBB63_4
+; RV32-NEXT: .LBB65_2: # %entry
+; RV32-NEXT: beqz a0, .LBB65_4
; RV32-NEXT: # %bb.3: # %overflow
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
-; RV32-NEXT: .LBB63_4: # %continue
+; RV32-NEXT: .LBB65_4: # %continue
; RV32-NEXT: li a0, 1
; RV32-NEXT: ret
;
; RV64-LABEL: umulo2.br.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: add a1, a0, a0
-; RV64-NEXT: bgeu a1, a0, .LBB63_2
+; RV64-NEXT: bgeu a1, a0, .LBB65_2
; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
-; RV64-NEXT: .LBB63_2: # %continue
+; RV64-NEXT: .LBB65_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
;
@@ -3919,26 +4007,26 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
; RV32ZBA-NEXT: sltu a0, a2, a0
; RV32ZBA-NEXT: add a2, a1, a1
; RV32ZBA-NEXT: add a2, a2, a0
-; RV32ZBA-NEXT: beq a2, a1, .LBB63_2
+; RV32ZBA-NEXT: beq a2, a1, .LBB65_2
; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: sltu a0, a2, a1
-; RV32ZBA-NEXT: .LBB63_2: # %entry
-; RV32ZBA-NEXT: beqz a0, .LBB63_4
+; RV32ZBA-NEXT: .LBB65_2: # %entry
+; RV32ZBA-NEXT: beqz a0, .LBB65_4
; RV32ZBA-NEXT: # %bb.3: # %overflow
; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret
-; RV32ZBA-NEXT: .LBB63_4: # %continue
+; RV32ZBA-NEXT: .LBB65_4: # %continue
; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret
;
; RV64ZBA-LABEL: umulo2.br.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: add a1, a0, a0
-; RV64ZBA-NEXT: bgeu a1, a0, .LBB63_2
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB65_2
; RV64ZBA-NEXT: # %bb.1: # %overflow
; RV64ZBA-NEXT: li a0, 0
; RV64ZBA-NEXT: ret
-; RV64ZBA-NEXT: .LBB63_2: # %continue
+; RV64ZBA-NEXT: .LBB65_2: # %continue
; RV64ZBA-NEXT: li a0, 1
; RV64ZBA-NEXT: ret
entry:
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