[llvm] cb5c4a5 - [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue, 4> width to avoid MSVC AVX alignment bug

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-04-01T10:54:24+01:00
New Revision: cb5c4a5917889bd12c5662c8b550cde11924d570

URL: https://github.com/llvm/llvm-project/commit/cb5c4a5917889bd12c5662c8b550cde11924d570
DIFF: https://github.com/llvm/llvm-project/commit/cb5c4a5917889bd12c5662c8b550cde11924d570.diff

LOG: [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue, 4> width to avoid MSVC AVX alignment bug

As discussed on Issue #54645 - building llc with /AVX can result in incorrectly aligned structs

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 56647db51ba1b..721ccac92a397 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -15838,7 +15838,8 @@ static SDValue lowerV8I16Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
       V1 = extract128BitVector(V1V2, 0, DAG, DL);
       V2 = extract128BitVector(V1V2, 4, DAG, DL);
     } else {
-      SmallVector<SDValue> DWordClearOps(4, DAG.getConstant(0, DL, MVT::i32));
+      SmallVector<SDValue, 4> DWordClearOps(4,
+                                            DAG.getConstant(0, DL, MVT::i32));
       for (unsigned i = 0; i != 4; i += 1 << (NumEvenDrops - 1))
         DWordClearOps[i] = DAG.getConstant(0xFFFF, DL, MVT::i32);
       SDValue DWordClearMask =