[PATCH] D122850: [AMDGPU] Fix regression with vectorization limiting

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 419586.
rampitec added a comment.

I have realized that RCID passed into getNumberOfRegisters(unsigned RCID) is in fact not an RCID, but boolean for vector/scalar registers. We could implement getRegisterClassForType() to change that, but we cannot reasonably distinguish between VGPRs and SGPRs anyway. At the end result is clamped to just 4, so it is easier to remove all of these calculations and simply return 4.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122850/new/

https://reviews.llvm.org/D122850

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll
  llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll

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