[llvm] 2e55bc9 - [PowerPC] Set the special DSCR with a compiler option.
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 31 12:06:35 PDT 2022
Author: Stefan Pintilie
Date: 2022-03-31T14:06:30-05:00
New Revision: 2e55bc9f3c233679535e237623539195e6492ec1
URL: https://github.com/llvm/llvm-project/commit/2e55bc9f3c233679535e237623539195e6492ec1
DIFF: https://github.com/llvm/llvm-project/commit/2e55bc9f3c233679535e237623539195e6492ec1.diff
LOG: [PowerPC] Set the special DSCR with a compiler option.
Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be set by default.
Original patch by: Muhammad Usman
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D117013
Added:
llvm/test/CodeGen/PowerPC/dscr-set.ll
Modified:
llvm/lib/Target/PowerPC/P10InstrResources.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/test/MC/PowerPC/ppc64-encoding-ext.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index 7aaac73ec9632..b3a91df2e8a0f 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -1372,7 +1372,7 @@ def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read]
LDCIX,
LHZCIX,
LWZCIX,
- MTSPR, MTSPR8, MTSR, MTVRSAVE, MTVRSAVEv
+ MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv
)>;
// Expand instructions
@@ -1469,7 +1469,7 @@ def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C],
// 13 Cycles Unknown operations, 1 input operands
def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY],
(instrs
- MFSPR, MFSPR8, MFSR, MFTB8, MFVRSAVE, MFVRSAVEv
+ MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv
)>;
// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 736a8a04ca31a..acb3585156ed7 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -932,6 +932,7 @@ def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
(instregex "M(T|F)TB(8)?$"),
(instregex "MF(SPR|CTR|LR)(8)?$"),
(instregex "M(T|F)MSR(D)?$"),
+ (instregex "M(T|F)(U)?DSCR$"),
(instregex "MTSPR(8)?$")
)>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 961f9e3d51c7e..27730aac33168 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3069,6 +3069,22 @@ def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
}
}
+let hasSideEffects = 1 in {
+ def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX),
+ "mtspr 3, $rX", IIC_SprMTSPR>,
+ PPC970_DGroup_Single, PPC970_Unit_FXU;
+ def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins),
+ "mfspr $rX, 3", IIC_SprMFSPR>,
+ PPC970_DGroup_First, PPC970_Unit_FXU;
+}
+
+// Disable these alias on AIX since they are not supported.
+let Predicates = [ModernAs] in {
+// Aliases for moving to/from dscr to mtspr/mfspr
+def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>;
+def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>;
+}
+
let isCodeGenOnly = 1 in {
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
// like a GPR on the PPC970. As such, copies in and out have the same
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index a8853609a7c87..82c150b988ab8 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@@ -46,6 +47,10 @@ static cl::opt<bool>
RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
cl::desc("Run pre-emit peephole optimizations."));
+static cl::opt<uint64_t>
+DSCRValue("ppc-set-dscr", cl::Hidden,
+ cl::desc("Set the Data Stream Control Register."));
+
namespace {
static bool hasPCRelativeForm(MachineInstr &Use) {
@@ -407,6 +412,38 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
}
bool runOnMachineFunction(MachineFunction &MF) override {
+ // If the user wants to set the DSCR using command-line options,
+ // load in the specified value at the start of main.
+ if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
+ MF.getFunction().hasExternalLinkage()) {
+ DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
+ RegScavenger RS;
+ MachineBasicBlock &MBB = MF.front();
+ // Find an unused GPR according to register liveness
+ RS.enterBasicBlock(MBB);
+ unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass);
+ if (InDSCR) {
+ const PPCInstrInfo *TII =
+ MF.getSubtarget<PPCSubtarget>().getInstrInfo();
+ DebugLoc dl;
+ MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point
+ // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and
+ // ORI, then move to DSCR. If the requested DSCR value is contained
+ // in a 16-bit signed number, we can emit a single `LI`, but the
+ // impact of saving one instruction in one function does not warrant
+ // any additional complexity in the logic here.
+ BuildMI(MBB, IP, dl, TII->get(PPC::LIS), InDSCR)
+ .addImm(DSCRValue >> 16);
+ BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR)
+ .addReg(InDSCR)
+ .addImm(DSCRValue & 0xFFFF);
+ BuildMI(MBB, IP, dl, TII->get(PPC::MTUDSCR))
+ .addReg(InDSCR, RegState::Kill);
+ } else
+ errs() << "Warning: Ran out of registers - Unable to set DSCR as "
+ "requested";
+ }
+
if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
// Remove UNENCODED_NOP even when this pass is disabled.
// This needs to be done unconditionally so we don't emit zeros
diff --git a/llvm/test/CodeGen/PowerPC/dscr-set.ll b/llvm/test/CodeGen/PowerPC/dscr-set.ll
new file mode 100644
index 0000000000000..8948dde666ae5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/dscr-set.ll
@@ -0,0 +1,23 @@
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN: | FileCheck %s -check-prefix=DEFAULT
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN: -ppc-set-dscr=0xFFFFFFFFFFFFFFFF | FileCheck %s -check-prefix=UPPER
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN: -ppc-set-dscr=0x01C4 | FileCheck %s -check-prefix=LOWER
+
+define i32 @main() {
+
+; CHECK: # %bb.0:
+
+; DEFAULT-NOT: mtudscr
+
+; UPPER: lis [[inReg:[0-9]+]], 511
+; UPPER-NEXT: ori [[inReg]], [[inReg]], 65535
+; UPPER-NEXT: mtudscr [[inReg]]
+
+; LOWER: lis [[inReg:[0-9]+]], 0
+; LOWER-NEXT: ori [[inReg]], [[inReg]], 452
+; LOWER-NEXT: mtudscr [[inReg]]
+
+ ret i32 1
+}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
index ca72b7cf5b7c2..c79e20b31f948 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -847,6 +847,12 @@
# CHECK: mfspr 2, 600
0x7c 0x58 0x92 0xa6
+# CHECK: mtudscr 2
+0x7c 0x43 0x03 0xa6
+
+# CHECK: mfudscr 2
+0x7c 0x43 0x02 0xa6
+
# CHECK: mtcrf 123, 2
0x7c 0x47 0xb1 0x20
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
index d6aa6b836b24d..959f3c53b0a19 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -3431,6 +3431,12 @@
# CHECK-BE: mfrtcl 2 # encoding: [0x7c,0x45,0x02,0xa6]
# CHECK-LE: mfrtcl 2 # encoding: [0xa6,0x02,0x45,0x7c]
mfrtcl 2
+# CHECK-BE: mtudscr 2 # encoding: [0x7c,0x43,0x03,0xa6]
+# CHECK-LE: mtudscr 2 # encoding: [0xa6,0x03,0x43,0x7c]
+ mtudscr 2
+# CHECK-BE: mfudscr 2 # encoding: [0x7c,0x43,0x02,0xa6]
+# CHECK-LE: mfudscr 2 # encoding: [0xa6,0x02,0x43,0x7c]
+ mfudscr 2
# CHECK-BE: mtdscr 2 # encoding: [0x7c,0x51,0x03,0xa6]
# CHECK-LE: mtdscr 2 # encoding: [0xa6,0x03,0x51,0x7c]
mtdscr 2
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