[PATCH] D122287: [XCOFF] support writing sections, relocations and symbols for XCOFF64.

[Digger Lin via Phabricator via llvm-commits]

DiggerLin added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp:82
+    case MCSymbolRefExpr::VK_None:
+      return {XCOFF::RelocationType::R_TOC, 15};
+    case MCSymbolRefExpr::VK_PPC_L:
----------------
DiggerLin wrote:
> Esme wrote:
> > DiggerLin wrote:
> > > I am not sure, whether I understand correct or not ?
> > > 1. fixup_ppc_half16ds: A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
> > > 2. fixup_ppc_half16dq:  A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
> > > 3. fixup_ppc_half16 : A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
> > > 
> > > in the https://www.ibm.com/docs/en/aix/7.2?topic=formats-xcoff-object-file-format#XCOFF__sua3i125jbau 
> > > r_rsize: 0x3F(6 bits)
> > > Specifies the bit length of the relocatable reference **minus one**. The current architecture allows for fields of up to 32 bits (XCOFF32) or 64 bits (XCOFF64) to be relocated.
> > > 
> > > so for the
> > > case PPC::fixup_ppc_half16ds: 
> > >     {XCOFF::RelocationType::R_TOC, EncodedSignednessIndicator | 13 } 
> > Thanks for your catch!
> PPC::fixup_ppc_half16dq: is a A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'. 
> for  PPC::fixup_ppc_half16dq 
> it should be 
> {XCOFF::RelocationType::R_TOC, EncodedSignednessIndicator | 15 } ?
I am not a expert on the relocation, I just put my question and we may be need someone who is expert on the relocation to review the code.



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  https://reviews.llvm.org/D122287/new/

https://reviews.llvm.org/D122287