[PATCH] D122829: [AArch64] Optimize SDIV with pow2 constant divisor

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

In D122829#3419777 <https://reviews.llvm.org/D122829#3419777>, @craig.topper wrote:

> Does this differ in an important way from what you get if you remove BuildSDIVPow2? I think you'll get sign bit shifted all the way to the right followed by a lsr. While this patch will shift the sign bit only as far as it needs to.

remove BuildSDIVPow2 also works for scalar cases. But test failed on sve cases. 
I can also shift 31/63 everytime but I think currect code is also correct.


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