[PATCH] D122796: [SVE][AArch64] Enable first active true vector combine for INTRINSIC_WO_CHAIN

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 31 09:23:57 PDT 2022


paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14519
+      (SetCC.getOpcode() != ISD::SETCC &&
+       SetCC.getOpcode() != ISD::INTRINSIC_WO_CHAIN))
     return SDValue();
----------------
david-arm wrote:
> paulwalker-arm wrote:
> > david-arm wrote:
> > > Hi @Allen, don't you also have to check the first operand to see if it matches the intrinsic, i.e. aarch64_sve_whilelo or aarch64_sve_whilels?
> > I guess I should have asked this a couple of patches ago but being provocative what's the value in having any restriction here?  I recall something about allowing hoisting from loops but is this really a necessary consideration at this phase of compilation? Are there other things to consider?
> So I think the MachineLICM pass runs after this phase, right? And if you introduce flag-setting operations they don't get hoisted out. Obviously if you had flag-setting operations to start with then it's no worse. This is what happens when you dup a i1 into a predicate register, for example see LowerSPLAT_VECTOR where we create a whilelo that then never gets hoisted out of the loop.
> 
> I'm happy to be proved wrong though as I may have missed something!
Sure, that makes sense. I guess what I'm asking is what's the scenario where we are extracting from a loop invariant predicate vector that hasn't already been hoisted at the IR level.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122796/new/

https://reviews.llvm.org/D122796



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