[llvm] f1cb816 - [AArch64][SVE] Mark {CNT*, RDVL, INDEX} as materializable

[Peter Waller via llvm-commits]

Author: Peter Waller
Date: 2022-03-31T15:28:24Z
New Revision: f1cb816f90859af971c30ee19ecfbc81be8fde5e

URL: https://github.com/llvm/llvm-project/commit/f1cb816f90859af971c30ee19ecfbc81be8fde5e
DIFF: https://github.com/llvm/llvm-project/commit/f1cb816f90859af971c30ee19ecfbc81be8fde5e.diff

LOG: [AArch64][SVE] Mark {CNT*,RDVL,INDEX} as materializable

Differential Revision: https://reviews.llvm.org/D122731

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/SVEInstrFormats.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index b5bb0cab9d1e2..be27d81433b2e 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -913,6 +913,8 @@ class sve_int_count<bits<3> opc, string asm>
   let Inst{10}    = opc{0};
   let Inst{9-5}   = pattern;
   let Inst{4-0}   = Rd;
+
+  let isReMaterializable = 1;
 }
 
 multiclass sve_int_count<bits<3> opc, string asm, SDPatternOperator op> {
@@ -2539,6 +2541,8 @@ class sve_int_read_vl_a<bit op, bits<5> opc2, string asm, bit streaming_sve = 0b
   let Inst{11}    = streaming_sve;
   let Inst{10-5}  = imm6;
   let Inst{4-0}   = Rd;
+
+  let isReMaterializable = 1;
 }
 
 //===----------------------------------------------------------------------===//
@@ -5190,6 +5194,8 @@ class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
   let Inst{15-10} = 0b010000;
   let Inst{9-5}   = imm5;
   let Inst{4-0}   = Zd;
+
+  let isReMaterializable = 1;
 }
 
 multiclass sve_int_index_ii<string asm> {