[PATCH] D122829: [AArch64] Optimize SDIV with pow2 constant divisor

[chenglin.bi via Phabricator via llvm-commits]

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SRA/SRL instead CMP/CSEL in SDIV with pow2 const divisor's folding.

Fix https://github.com/llvm/llvm-project/issues/54649


https://reviews.llvm.org/D122829

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/fast-isel-sdiv.ll
  llvm/test/CodeGen/AArch64/sdivpow2.ll
  llvm/test/CodeGen/AArch64/srem-lkk.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

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