[PATCH] D122796: [SVE][AArch64] Enable first active true vector combine for INTRINSIC_WO_CHAIN

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14519
+      (SetCC.getOpcode() != ISD::SETCC &&
+       SetCC.getOpcode() != ISD::INTRINSIC_WO_CHAIN))
     return SDValue();
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Hi @Allen, don't you also have to check the first operand to see if it matches the intrinsic, i.e. aarch64_sve_whilelo or aarch64_sve_whilels?


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Comment at: llvm/test/CodeGen/AArch64/sve-cmp-folds.ll:39
+; CHECK-NEXT:    ret
+  %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64 %next, i64 %end)
+  %bit = extractelement <vscale x 4 x i1> %predicate, i64 0
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Since you also want to support the DAG combine with whilels is it worth having a test for that too?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122796/new/

https://reviews.llvm.org/D122796