[PATCH] D122672: [CodeGen][ARM] Enable Swing Module Scheduling for ARM

[Dave Green via Phabricator via llvm-commits]

dmgreen added a reviewer: kparzysz.
dmgreen added a comment.

Sounds like a nice addition.



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Comment at: llvm/lib/CodeGen/MachinePipeliner.cpp:1671
                    << TRI->getRegPressureSetName(RPDelta.Excess.getPSet())
-                   << ":" << RPDelta.Excess.getUnitInc());
+                   << ":" << RPDelta.Excess.getUnitInc() << "\n");
         NS.setExceedPressure(SU);
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Can you take the NFC cleanup and spelling fixes and commit those separately. They look like good fixes on their own.


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Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:504
         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
-    } else
+    } else if (Cond.size() == 2)
       BuildMI(&MBB, DL, get(BccOpc))
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Are these changes for removeBranch/insertBranch/reverseBranchCondition etc needed here, or should they be part of the patch that adds analyzeBranch for t2LoopEnd?


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Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:6767
+    } else {
+      assert(false && "Unknown EndLoop");
+    }
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I think it's usually preferred to use llvm_unreachable to assert(false)


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Comment at: llvm/test/CodeGen/ARM/O3-pipeline.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
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This looks like it should be removed.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D122672/new/

https://reviews.llvm.org/D122672