[llvm] 2f1261a - [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
ShihPo Hung via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 31 01:38:52 PDT 2022
Author: ShihPo Hung
Date: 2022-03-31T01:33:17-07:00
New Revision: 2f1261abe4b704781ed1504065072d34d506f984
URL: https://github.com/llvm/llvm-project/commit/2f1261abe4b704781ed1504065072d34d506f984
DIFF: https://github.com/llvm/llvm-project/commit/2f1261abe4b704781ed1504065072d34d506f984.diff
LOG: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
This patch adds Uses = [FRM] and mayRaiseFPException = true to following
instructions:
VFADD, VFSUB, VFRSUB, VFMUL, VFDIV, VFRDIV
VFWADD, VFWSUB, VFWMUL
VFMADD, VFMACC, VFMSAC, VFMSUB
VFNMADD, VFNMACC, VFNMSAC, VVFNMSUB
VFWMACC, VFWMSAC,
VFWNMACC, VFWNMSAC
VFSQRT, VFREC7
VFREDOSUM, VFREDUSUM,
VFWREDOSUM, VFWREDUSUM
and only adds mayRaiseFPException = true to following instructions:
VFRSQRT7,
VFMIN, VFMAX, VFREDMIN, VFREDMAX
VMFEQ, VMFNE, VMFLT,VMFLE, VMFGT, VMFGE
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D121087
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 893d1f65413e9..f8bc241039f89 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1131,12 +1131,16 @@ defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
let Predicates = [HasVInstructionsAnyF] in {
// Vector Single-Width Floating-Point Add/Subtract Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
+}
// Vector Widening Floating-Point Add/Subtract Instructions
-let Constraints = "@earlyclobber $vd" in {
+let Constraints = "@earlyclobber $vd",
+ Uses = [FRM],
+ mayRaiseFPException = true in {
let RVVConstraint = WidenV in {
defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000>;
defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010>;
@@ -1149,19 +1153,23 @@ let RVVConstraint = WidenW in {
defm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">;
defm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">;
} // RVVConstraint = WidenW
-} // Constraints = "@earlyclobber $vd"
+} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true
// Vector Single-Width Floating-Point Multiply/Divide Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>;
defm VFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>;
defm VFRDIV_V : VRDIV_FV_F<"vfrdiv", 0b100001>;
+}
// Vector Widening Floating-Point Multiply
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
+ Uses = [FRM], mayRaiseFPException = true in {
defm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>;
defm VFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>;
defm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>;
@@ -1170,23 +1178,31 @@ defm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>;
defm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>;
defm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>;
defm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>;
+}
// Vector Widening Floating-Point Fused Multiply-Add Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
+ Uses = [FRM], mayRaiseFPException = true in {
defm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>;
defm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>;
defm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>;
defm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
// Vector Floating-Point Square-Root Instruction
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
-defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>;
defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>;
+}
+
+let mayRaiseFPException = true in
+defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>;
// Vector Floating-Point MIN/MAX Instructions
+let mayRaiseFPException = true in {
defm VFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>;
defm VFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>;
+}
// Vector Floating-Point Sign-Injection Instructions
defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>;
@@ -1203,14 +1219,14 @@ def : InstAlias<"vfabs.v $vd, $vs",
(VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
// Vector Floating-Point Compare Instructions
-let RVVConstraint = NoConstraint in {
+let RVVConstraint = NoConstraint, mayRaiseFPException = true in {
defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>;
defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>;
defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>;
defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>;
defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>;
defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>;
-} // RVVConstraint = NoConstraint
+} // RVVConstraint = NoConstraint, mayRaiseFPException = true
def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
(VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
@@ -1299,10 +1315,14 @@ defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
let Predicates = [HasVInstructionsAnyF] in {
// Vector Single-Width Floating-Point Reduction Instructions
let RVVConstraint = NoConstraint in {
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>;
defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>;
+}
+let mayRaiseFPException = true in {
defm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>;
defm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>;
+}
} // RVVConstraint = NoConstraint
def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
@@ -1314,8 +1334,10 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
+let Uses = [FRM], mayRaiseFPException = true in {
defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>;
+}
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 687ccd579be2c..c2c04add5e0b6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4586,33 +4586,42 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFADD : VPseudoVALU_VV_VF;
defm PseudoVFSUB : VPseudoVALU_VV_VF;
defm PseudoVFRSUB : VPseudoVALU_VF;
+}
//===----------------------------------------------------------------------===//
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFWADD : VPseudoVFWALU_VV_VF;
defm PseudoVFWSUB : VPseudoVFWALU_VV_VF;
defm PseudoVFWADD : VPseudoVFWALU_WV_WF;
defm PseudoVFWSUB : VPseudoVFWALU_WV_WF;
+}
//===----------------------------------------------------------------------===//
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFMUL : VPseudoVFMUL_VV_VF;
defm PseudoVFDIV : VPseudoVFDIV_VV_VF;
defm PseudoVFRDIV : VPseudoVFRDIV_VF;
+}
//===----------------------------------------------------------------------===//
// 14.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF;
+}
//===----------------------------------------------------------------------===//
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA;
defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA;
defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA;
@@ -4621,35 +4630,43 @@ defm PseudoVFMADD : VPseudoVMAC_VV_VF_AAXA;
defm PseudoVFNMADD : VPseudoVMAC_VV_VF_AAXA;
defm PseudoVFMSUB : VPseudoVMAC_VV_VF_AAXA;
defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA;
+}
//===----------------------------------------------------------------------===//
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFWMACC : VPseudoVWMAC_VV_VF;
defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF;
defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF;
defm PseudoVFWNMSAC : VPseudoVWMAC_VV_VF;
+}
//===----------------------------------------------------------------------===//
// 14.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in
defm PseudoVFSQRT : VPseudoVSQR_V;
//===----------------------------------------------------------------------===//
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in
defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in
defm PseudoVFREC7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 14.11. Vector Floating-Point Min/Max Instructions
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in {
defm PseudoVFMIN : VPseudoVMAX_VV_VF;
defm PseudoVFMAX : VPseudoVMAX_VV_VF;
+}
//===----------------------------------------------------------------------===//
// 14.12. Vector Floating-Point Sign-Injection Instructions
@@ -4661,12 +4678,14 @@ defm PseudoVFSGNJX : VPseudoVSGNJ_VV_VF;
//===----------------------------------------------------------------------===//
// 14.13. Vector Floating-Point Compare Instructions
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in {
defm PseudoVMFEQ : VPseudoVCMPM_VV_VF;
defm PseudoVMFNE : VPseudoVCMPM_VV_VF;
defm PseudoVMFLT : VPseudoVCMPM_VV_VF;
defm PseudoVMFLE : VPseudoVCMPM_VV_VF;
defm PseudoVMFGT : VPseudoVCMPM_VF;
defm PseudoVMFGE : VPseudoVCMPM_VF;
+}
//===----------------------------------------------------------------------===//
// 14.14. Vector Floating-Point Classify Instruction
@@ -4743,15 +4762,21 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
+let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS;
defm PseudoVFREDUSUM : VPseudoVFRED_VS;
+}
+let mayRaiseFPException = true in {
defm PseudoVFREDMIN : VPseudoVFRED_VS;
defm PseudoVFREDMAX : VPseudoVFRED_VS;
+}
//===----------------------------------------------------------------------===//
// 15.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-let IsRVVWideningReduction = 1 in {
+let IsRVVWideningReduction = 1,
+ Uses = [FRM],
+ mayRaiseFPException = true in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS;
defm PseudoVFWREDOSUM : VPseudoVFWRED_VS;
}
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