[PATCH] D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb updated this revision to Diff 419343.
arcbbb added a comment.

Address Craig's comments.
Updates:

1. Add assertions to check hasVL & hasSEW
2. Remove RISCVReg 'vcsr'
3. Do not mask immediate value
4. Fix inconsistent comments
5. Update O0 & O3 <https://reviews.llvm.org/owners/package/3/> pipeline tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121376/new/

https://reviews.llvm.org/D121376

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/RISCVVXRMRegister.cpp
  llvm/test/CodeGen/RISCV/O0-pipeline.ll
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/rvv/roundmode-insert.ll
  llvm/test/CodeGen/RISCV/rvv/roundmode-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vaadd-rm-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaadd-rm-rv64.ll

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