[PATCH] D122769: [RISCV] Add a prepass to vsetvli insertion to propagate VLMAX vsetvli to the instructions.

[Craig Topper via Phabricator via llvm-commits]

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If the VL value for a vector instruction comes from a vsetvli for
VLMAX and the SEW/LMUL ratio matches, we can replace the VL on the
instruction with X0. This allows all the vsetvlis generated for the
instruction to use VLMAX vsetvlis. Or it can prevent vsetvli
instructions from being generated in loops.

This is based on a test case rogfer01 sent me a while back. We could
propagate any AVL, but looking at some of the test changes for that
I'm not sure it makes sense. So I've restricted to just the VLMAX case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122769

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

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