[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

[Sam Elliott via Phabricator via llvm-commits]

lenary planned changes to this revision.
lenary added inline comments.


================
Comment at: llvm/lib/CodeGen/RDFGraph.cpp:1096
     RegisterRef RR = PDA.Addr->getRegRef(*this);
-#ifndef NDEBUG
-    // Assert if the register is defined in two or more unrelated defs.
-    // This could happen if there are two or more def operands defining it.
-    if (!Defined.insert(RR.Reg).second) {
-      MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
-      dbgs() << "Multiple definitions of register: "
-             << Print<RegisterRef>(RR, *this) << " in\n  " << *MI << "in "
-             << printMBBReference(*MI->getParent()) << '\n';
-      llvm_unreachable(nullptr);
-    }
-#endif
+// #ifndef NDEBUG
+//     // Assert if the register is defined in two or more unrelated defs.
----------------
I forgot to remove these comments, will update shortly.


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Comment at: llvm/lib/Target/ARM/ARMSubtarget.h:543
   unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
+
 };
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I missed this, will update again shortly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119720/new/

https://reviews.llvm.org/D119720