[PATCH] D122702: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)

[Ben Shi via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4cb85da81124: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3) (authored by Miss_Grape, committed by benshi001).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122702/new/

https://reviews.llvm.org/D122702

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbt.ll
  llvm/test/CodeGen/RISCV/rv64zbt.ll

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