[PATCH] D122563: [RISCV] Add DAGCombine to fold base operation and reduction.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7273
+    if (Opc == ISD::FADD && N->getFlags().hasNoSignedZeros())
+      return isNullFPConstant(V);
+    return DAG.getNeutralElement(Opc, SDLoc(V), V.getSimpleValueType(),
----------------
craig.topper wrote:
> I think you want the isNullFPConstant in the `if` and a `return true` here. Just because hasNoSignedZeros is true doesn't mean that -0.0 can't appear.
When hasNoSignedZeros enabling, compiler insert +0.0 into VECREDUCE_FADD_VL. I think the only way to replace the start value is this combiner `combineBinOpToReduce`, so the start value is -0.0 is caused by FADD with -0.0. But I think DAGCombiner could fix it. 


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  https://reviews.llvm.org/D122563/new/

https://reviews.llvm.org/D122563