[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

[Zircon Liu via Phabricator via llvm-commits]

SForeKeeper added inline comments.


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Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:35
+PROC(XIANGSHAN_YANQIHU,{"xiangshan-yanqihu"},FK_64BIT,{"rv64gc"})
+PROC(XIANGSHAN_NANHU,{"xiangshan-nanhu"},FK_64BIT,{"rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh"})
 
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jrtc27 wrote:
> Why imafd rather than g?
The official document defines the default march as "RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval".

Using g is more sensible though.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:546
+
+def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit,
+                                                       FeatureStdExtM,
----------------
jrtc27 wrote:
> Isn't this still under development?
Yes, though not taped out, the RTL design is "basically" frozen according to their developers. 


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Comment at: llvm/lib/Target/RISCV/RISCV.td:547
+def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit,
+                                                       FeatureStdExtM,
+                                                       FeatureStdExtA,
----------------
StephenFan wrote:
> The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm.
> The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm.




================
Comment at: llvm/lib/Target/RISCV/RISCV.td:547
+def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit,
+                                                       FeatureStdExtM,
+                                                       FeatureStdExtA,
----------------
SForeKeeper wrote:
> StephenFan wrote:
> > The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm.
> > The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm.
> 
> 
Specifying `Svinval` here and in the `RISCVTargetParser.def` will require to implement it. (at least declaration is needed) 
Since `Svinval` is still at a very early stage, I suppose it shouldn't be declared here now.


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  https://reviews.llvm.org/D122556/new/

https://reviews.llvm.org/D122556