[llvm] 7f81765 - [RISCV][NFC] Add immediate tests for the icmp instruction
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 29 20:04:42 PDT 2022
Author: Liqin Weng
Date: 2022-03-30T02:51:26Z
New Revision: 7f817658980ebc464e59afe32b03d8d3d92346e0
URL: https://github.com/llvm/llvm-project/commit/7f817658980ebc464e59afe32b03d8d3d92346e0
DIFF: https://github.com/llvm/llvm-project/commit/7f817658980ebc464e59afe32b03d8d3d92346e0.diff
LOG: [RISCV][NFC] Add immediate tests for the icmp instruction
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D122651
Added:
llvm/test/CodeGen/RISCV/i64-icmp.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/i32-icmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2e65185a0b1d7..fdb1af9d558f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -352,7 +352,7 @@ def simm12_plus1 : ImmLeaf<XLenVT,
[{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
// A 12-bit signed immediate sub one and exclude zero
-def simm12_sub1_nonzero : PatLeaf<(imm), [{
+def simm12_minus1_nonzero : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
// The immediate operand must be in range [-2049, 0) or (0, 2046].
@@ -1217,10 +1217,10 @@ def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
-def : Pat<(setgt GPR:$rs1, simm12_sub1_nonzero:$imm),
- (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
-def : Pat<(setugt GPR:$rs1, simm12_sub1_nonzero:$imm),
- (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
+def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm),
+ (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
+def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm),
+ (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
index 9b543f103e56a..deb7dfd883bff 100644
--- a/llvm/test/CodeGen/RISCV/i32-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -2,9 +2,6 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; TODO: check the generated instructions for the equivalent of seqz, snez,
-; sltz, sgtz map to something simple
-
define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_eq:
; RV32I: # %bb.0:
@@ -27,6 +24,19 @@ define i32 @icmp_eq_constant(i32 %a) nounwind {
ret i32 %2
}
+define i32 @icmp_eq_constant_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_eq_constant_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2047
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp eq i32 %a, 2049
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_eq_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant_2048:
; RV32I: # %bb.0:
@@ -93,6 +103,19 @@ define i32 @icmp_ne_constant(i32 %a) nounwind {
ret i32 %2
}
+define i32 @icmp_ne_constant_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ne_constant_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2047
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp ne i32 %a, 2049
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ne_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_2048:
; RV32I: # %bb.0:
@@ -116,6 +139,17 @@ define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {
ret i32 %2
}
+define i32 @icmp_ne_constant_neg_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ne_constant_neg_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a0, a0, 2047
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp ne i32 %a, -2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_nez(i32 %a) nounwind {
; RV32I-LABEL: icmp_nez:
; RV32I: # %bb.0:
@@ -204,6 +238,63 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
ret i32 %2
}
+define i32 @icmp_uge_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_uge_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: ret
+ %1 = icmp uge i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_uge_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_uge_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, 2047
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+ %1 = icmp uge i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_uge_constant_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_uge_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 2047
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: ret
+ %1 = icmp uge i32 %a, 2048
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_uge_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, -2048
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+; 4294965248 signed extend is -2048
+ %1 = icmp uge i32 %a, 4294965248
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_uge_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2046
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp uge i32 %a, 4294965247
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult:
; RV32I: # %bb.0:
@@ -214,6 +305,61 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
ret i32 %2
}
+define i32 @icmp_ult_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: ret
+ %1 = icmp ult i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ult_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, 2047
+; RV32I-NEXT: ret
+ %1 = icmp ult i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ult_constant_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a0, a0, 11
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp ult i32 %a, 2048
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, -2048
+; RV32I-NEXT: ret
+; 4294965248 signed extend is -2048
+ %1 = icmp ult i32 %a, 4294965248
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2047
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp ult i32 %a, 4294965247
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule:
; RV32I: # %bb.0:
@@ -225,23 +371,67 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
ret i32 %2
}
-define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: icmp_sgt:
+define i32 @icmp_ule_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ule_constant_zero:
; RV32I: # %bb.0:
-; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
- %1 = icmp sgt i32 %a, %b
+ %1 = icmp ule i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
-define i32 @icmp_sgt_constant(i32 %a) nounwind {
-; RV32I-LABEL: icmp_sgt_constant:
+define i32 @icmp_ule_constant_2046(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ule_constant_2046:
; RV32I: # %bb.0:
-; RV32I-NEXT: slti a0, a0, 6
-; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: sltiu a0, a0, 2047
+; RV32I-NEXT: ret
+ %1 = icmp ule i32 %a, 2046
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ule_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ule_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a0, a0, 11
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp ule i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ule_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, -2048
+; RV32I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp ule i32 %a, 4294965247
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ule_constant_neg_2050:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2047
+; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret
- %1 = icmp sgt i32 %a, 5
+; 4294965246 signed extend is -2050
+ %1 = icmp ule i32 %a, 4294965246
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_sgt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: ret
+ %1 = icmp sgt i32 %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
@@ -312,6 +502,61 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
ret i32 %2
}
+define i32 @icmp_sge_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sge_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: srli a0, a0, 31
+; RV32I-NEXT: ret
+ %1 = icmp sge i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sge_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sge_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, 2047
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+ %1 = icmp sge i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sge_constant_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sge_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 2047
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: ret
+ %1 = icmp sge i32 %a, 2048
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sge_constant_neg_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sge_constant_neg_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, -2047
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+ %1 = icmp sge i32 %a, -2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sge_constant_neg_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sge_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: srli a0, a0, 31
+; RV32I-NEXT: ret
+ %1 = icmp sge i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_slt:
; RV32I: # %bb.0:
@@ -322,6 +567,60 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
ret i32 %2
}
+define i32 @icmp_slt_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_slt_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a0, a0, 31
+; RV32I-NEXT: ret
+ %1 = icmp slt i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_slt_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_slt_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, 2047
+; RV32I-NEXT: ret
+ %1 = icmp slt i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_slt_constant_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_slt_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2048
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: ret
+ %1 = icmp slt i32 %a, 2048
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_slt_constant_neg_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_slt_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, -2048
+; RV32I-NEXT: ret
+ %1 = icmp slt i32 %a, -2048
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_slt_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_slt_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2047
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: ret
+ %1 = icmp slt i32 %a, -2049
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sle:
; RV32I: # %bb.0:
@@ -333,4 +632,56 @@ define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
ret i32 %2
}
-; TODO: check variants with an immediate?
+define i32 @icmp_sle_constant_zero(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sle_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: ret
+ %1 = icmp sle i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sle_constant_2046(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sle_constant_2046:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, 2047
+; RV32I-NEXT: ret
+ %1 = icmp sle i32 %a, 2046
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sle_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sle_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2048
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: ret
+ %1 = icmp sle i32 %a, 2047
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sle_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sle_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slti a0, a0, -2048
+; RV32I-NEXT: ret
+ %1 = icmp sle i32 %a, -2049
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @icmp_sle_constant_neg_2050(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sle_constant_neg_2050:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2047
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: ret
+ %1 = icmp sle i32 %a, -2050
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
diff --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
new file mode 100644
index 0000000000000..cbd1d6a9a008e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -0,0 +1,701 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64I
+
+define i64 @icmp_eq(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eq_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_constant:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, -42
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, 42
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eq_constant_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_constant_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2047
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, 2049
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eq_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, -2048
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, -2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eq_constant_neg_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_constant_neg_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, -2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_eqz(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eqz:
+; RV64I: # %bb.0:
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp eq i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_constant:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, -42
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, 42
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne_constant_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_constant_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2047
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, 2049
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, -2048
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, -2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ne_constant_neg_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_constant_neg_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, -2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_nez(i64 %a) nounwind {
+; RV64I-LABEL: icmp_nez:
+; RV64I: # %bb.0:
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_ugt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp ugt i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ugt_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ugt i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ugt_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 2047
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp ugt i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt_constant_2046(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ugt_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a0, a0, 2047
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp ugt i64 %a, 2046
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ugt_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1046527
+; RV64I-NEXT: slli a1, a1, 20
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp ugt i64 %a, 4294965247
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ugt_constant_neg_2050:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, -1025
+; RV64I-NEXT: slli a1, a1, 33
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+; 4294965246 signed extend is -2050
+ %1 = icmp ugt i64 %a, 4294965246
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp uge i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_uge_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp uge i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_uge_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a0, a0, 2047
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp uge i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_uge_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 2047
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp uge i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_uge_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1046527
+; RV64I-NEXT: slli a1, a1, 20
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+; 4294965248 signed extend is -2048
+ %1 = icmp uge i64 %a, 4294965248
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_uge_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, -1025
+; RV64I-NEXT: slli a1, a1, 33
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp uge i64 %a, 4294965247
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_ult:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp ult i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ult_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: ret
+ %1 = icmp ult i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ult_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a0, a0, 2047
+; RV64I-NEXT: ret
+ %1 = icmp ult i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ult_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a0, a0, 11
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ult i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ult_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 1
+; RV64I-NEXT: slli a1, a1, 32
+; RV64I-NEXT: addi a1, a1, -2048
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: ret
+; 4294965248 signed extend is -2048
+ %1 = icmp ult i64 %a, 4294965248
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ult_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1046527
+; RV64I-NEXT: slli a1, a1, 20
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp ult i64 %a, 4294965247
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp ule i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ule_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ule i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule_constant_2046(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ule_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a0, a0, 2047
+; RV64I-NEXT: ret
+ %1 = icmp ule i64 %a, 2046
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ule_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a0, a0, 11
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp ule i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ule_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 1
+; RV64I-NEXT: slli a1, a1, 32
+; RV64I-NEXT: addi a1, a1, -2048
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: ret
+; 4294965247 signed extend is -2049
+ %1 = icmp ule i64 %a, 4294965247
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ule_constant_neg_2050:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1046527
+; RV64I-NEXT: slli a1, a1, 20
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: ret
+; 4294965246 signed extend is -2050
+ %1 = icmp ule i64 %a, 4294965246
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_sgt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sgt_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sgtz a0, a0
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt_constant_2046(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sgt_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, 2047
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, 2046
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sgt_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 2047
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sgt_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, -2048
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, -2049
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sgt_constant_neg_2050:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2046
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp sgt i64 %a, -2050
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_sge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sge_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: srli a0, a0, 63
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sge_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, 2047
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sge_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 2047
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge_constant_neg_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sge_constant_neg_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, -2047
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, -2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sge_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sge_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: srli a0, a0, 63
+; RV64I-NEXT: ret
+ %1 = icmp sge i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_slt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_slt_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a0, a0, 63
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_slt_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, 2047
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt_constant_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_slt_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, 2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind {
+; RV64I-LABEL: icmp_slt_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, -2048
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, -2048
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_slt_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp slt i64 %a, -2049
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: icmp_sle:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, %b
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle_constant_zero(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sle_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, 0
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle_constant_2046(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sle_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, 2047
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, 2046
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle_constant_2047(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sle_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, 2047
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sle_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slti a0, a0, -2048
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, -2049
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
+define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
+; RV64I-LABEL: icmp_sle_constant_neg_2050:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: ret
+ %1 = icmp sle i64 %a, -2050
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
More information about the llvm-commits
mailing list