[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori
LiqinWeng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 29 19:02:38 PDT 2022
Miss_Grape updated this revision to Diff 419036.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D122051/new/
https://reviews.llvm.org/D122051
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
llvm/test/CodeGen/RISCV/float-fcmp.ll
llvm/test/CodeGen/RISCV/i32-icmp.ll
llvm/test/CodeGen/RISCV/i64-icmp.ll
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/xaluo.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D122051.419036.patch
Type: text/x-patch
Size: 28527 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220330/50248c5f/attachment-0001.bin>
More information about the llvm-commits
mailing list