[PATCH] D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

Tue Mar 29 09:04:31 PDT 2022

lewis-revill added a comment.

In D76007#3412660 <https://reviews.llvm.org/D76007#3412660>, @arsenm wrote:

> In D76007#3412653 <https://reviews.llvm.org/D76007#3412653>, @arsenm wrote:
>
>> In D76007#3310559 <https://reviews.llvm.org/D76007#3310559>, @lewis-revill wrote:
>>
>>> In D76007#3308144 <https://reviews.llvm.org/D76007#3308144>, @arsenm wrote:
>>>
>>>> Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.
>>>
>>> Right. But before this patch there was a max size associated to the bank itself, which is queried by the verifier. And if we want to keep that concept of a maximum size surely we should have it be accurate? So for different hardware modes it should be possible for it to be different.
>>
>> Why is there a maximum size concept? What is it used for? I haven't noticed thisb efore
>
> If it is a maximum, why can't you set to the maximum possible size?

Because this size isn't 'set' by a target, it's determined by tablegen to be the maximum size of the register **class** covered by the register bank. So for the RISC-V GPR banks that size will always depend on hardware mode, and as such the bank size **should** also reflect that - that's what this patch addresses.

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https://reviews.llvm.org/D76007