[PATCH] D122644: [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)
LiqinWeng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 29 04:05:20 PDT 2022
Miss_Grape updated this revision to Diff 418837.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D122644/new/
https://reviews.llvm.org/D122644
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/select-cc.ll
Index: llvm/test/CodeGen/RISCV/select-cc.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-cc.ll
+++ llvm/test/CodeGen/RISCV/select-cc.ll
@@ -105,7 +105,7 @@
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: slti a3, a2, 1
; RV32IBT-NEXT: cmov a0, a3, a0, a2
-; RV32IBT-NEXT: sltz a2, a2
+; RV32IBT-NEXT: slti a2, a2, 0
; RV32IBT-NEXT: cmov a0, a2, a1, a0
; RV32IBT-NEXT: ret
%val1 = load volatile i32, i32* %b
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -970,10 +970,11 @@
def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
-// setge X, 0 is canonicalized to setgt X, -1.
-// FIXME: This can be generalized to more immediates by using SLTI.
-def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
+// setge X, Imm is canonicalized to setgt X, (Imm - 1).
+def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -352,7 +352,7 @@
[{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
// A 12-bit signed immediate sub one and exclude zero
-def simm12_sub1_nonzero : PatLeaf<(imm), [{
+def simm12_minus1_nonzero : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
// The immediate operand must be in range [-2049, 0) or (0, 2046].
@@ -1217,10 +1217,10 @@
def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
-def : Pat<(setgt GPR:$rs1, simm12_sub1_nonzero:$imm),
- (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
-def : Pat<(setugt GPR:$rs1, simm12_sub1_nonzero:$imm),
- (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
+def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm),
+ (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
+def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm),
+ (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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