[PATCH] D122637: [RISCV] Trim RVV isel pats matchable via DAG post-process

[Fraser Cormack via Phabricator via llvm-commits]

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In D122512 <https://reviews.llvm.org/D122512>, several masked patterns were added to support lowering of
vector-predicated float-to-int and int-to-float conversions. With the
introduction of these patterns, all of the old "unmasked" patterns are
matchable via the DAG post-process introduced in D118810 <https://reviews.llvm.org/D118810>, once the relevant
opcode entries are set up in the helper table.

Locally this reduces the generated isel table by 4%.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122637

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

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