[llvm] 45e85fe - [RISCV] Pull APInt/computeKnonwbits specifics out of computeGREVOrGORC. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-03-28T20:53:54-07:00
New Revision: 45e85feba6e49a4d3257b78f1a50f94b3c79a492

URL: https://github.com/llvm/llvm-project/commit/45e85feba6e49a4d3257b78f1a50f94b3c79a492
DIFF: https://github.com/llvm/llvm-project/commit/45e85feba6e49a4d3257b78f1a50f94b3c79a492.diff

LOG: [RISCV] Pull APInt/computeKnonwbits specifics out of computeGREVOrGORC. NFC

This function now takes a uint64_t instead of an APInt. The caller
is responsible for masking the shift amount, extracting and inserting
into the KnownBits APInts, and inverting to compute zeros.

This is less code and cleaner division of responsibilities.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f110118f5253c..54aad0a70b621 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8914,19 +8914,11 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
   return UseMask(NewMask);
 }
 
-static void computeGREVOrGORC(APInt &Src, unsigned ShAmt, bool IsGORC,
-                              bool ComputeZeros = false) {
+static uint64_t computeGREVOrGORC(uint64_t x, unsigned ShAmt, bool IsGORC) {
   static const uint64_t GREVMasks[] = {
       0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL,
       0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL};
 
-  ShAmt &= Src.getBitWidth() - 1;
-  uint64_t x = Src.getZExtValue();
-
-  // To compute zeros, we need to invert the value and invert it back after.
-  if (ComputeZeros)
-    x = ~x;
-
   for (unsigned Stage = 0; Stage != 6; ++Stage) {
     unsigned Shift = 1 << Stage;
     if (ShAmt & Shift) {
@@ -8938,10 +8930,7 @@ static void computeGREVOrGORC(APInt &Src, unsigned ShAmt, bool IsGORC,
     }
   }
 
-  if (ComputeZeros)
-    x = ~x;
-
-  Src = x;
+  return x;
 }
 
 void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
@@ -9010,11 +8999,12 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   case RISCVISD::GORC: {
     if (auto *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
-      unsigned ShAmt = C->getZExtValue();
+      unsigned ShAmt = C->getZExtValue() & (Known.getBitWidth() - 1);
       bool IsGORC = Op.getOpcode() == RISCVISD::GORC;
-      computeGREVOrGORC(Known.Zero, ShAmt, IsGORC,
-                        /*ComputeZeros*/ true);
-      computeGREVOrGORC(Known.One, ShAmt, IsGORC);
+      // To compute zeros, we need to invert the value and invert it back after.
+      Known.Zero =
+          ~computeGREVOrGORC(~Known.Zero.getZExtValue(), ShAmt, IsGORC);
+      Known.One = computeGREVOrGORC(Known.One.getZExtValue(), ShAmt, IsGORC);
     }
     break;
   }