[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori
LiqinWeng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 28 20:04:13 PDT 2022
Miss_Grape updated this revision to Diff 418768.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D122051/new/
https://reviews.llvm.org/D122051
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
llvm/test/CodeGen/RISCV/float-fcmp.ll
llvm/test/CodeGen/RISCV/i32-icmp.ll
llvm/test/CodeGen/RISCV/i64-icmp.ll
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/xaluo.ll
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