[llvm] 2b3becb - [AArch64][GlobalISel] Add new MOVI pattern for fp constants
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Mon Mar 28 19:57:42 PDT 2022
Author: zhongyunde
Date: 2022-03-29T10:57:22+08:00
New Revision: 2b3becb41d2b3f2931f78643af23ce9a3842ab52
URL: https://github.com/llvm/llvm-project/commit/2b3becb41d2b3f2931f78643af23ce9a3842ab52
DIFF: https://github.com/llvm/llvm-project/commit/2b3becb41d2b3f2931f78643af23ce9a3842ab52.diff
LOG: [AArch64][GlobalISel] Add new MOVI pattern for fp constants
GlobalISel is used in option -O0, so add MOVI pattern for it,
which is done similar in gcc.(https://godbolt.org/z/8j6fzG3h6)
Fix https://github.com/llvm/llvm-project/issues/53651
Reviewed By: dmgreen, paquette
Differential Revision: https://reviews.llvm.org/D122559
Added:
llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 74dccb85a66eb..38049d4f6344c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1248,6 +1248,9 @@ def gi_fpimm32 : GICustomOperandRenderer<"renderFPImm32">,
GISDNodeXFormEquiv<fpimm32XForm>;
def gi_fpimm64 : GICustomOperandRenderer<"renderFPImm64">,
GISDNodeXFormEquiv<fpimm64XForm>;
+def gi_fpimm32SIMDModImmType4 :
+ GICustomOperandRenderer<"renderFPImm32SIMDModImmType4">,
+ GISDNodeXFormEquiv<fpimm32SIMDModImmType4XForm>;
// Vector lane operands
class AsmVectorIndex<int Min, int Max, string NamePrefix=""> : AsmOperandClass {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9c7015733d318..b215678d2e436 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -437,6 +437,9 @@ class AArch64InstructionSelector : public InstructionSelector {
int OpIdx = -1) const;
void renderFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx = -1) const;
+ void renderFPImm32SIMDModImmType4(MachineInstrBuilder &MIB,
+ const MachineInstr &MI,
+ int OpIdx = -1) const;
// Materialize a GlobalValue or BlockAddress using a movz+movk sequence.
void materializeLargeCMVal(MachineInstr &I, const Value *V, unsigned OpFlags);
@@ -6854,6 +6857,17 @@ void AArch64InstructionSelector::renderFPImm64(MachineInstrBuilder &MIB,
AArch64_AM::getFP64Imm(MI.getOperand(1).getFPImm()->getValueAPF()));
}
+void AArch64InstructionSelector::renderFPImm32SIMDModImmType4(
+ MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
+ assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 &&
+ "Expected G_FCONSTANT");
+ MIB.addImm(AArch64_AM::encodeAdvSIMDModImmType4(MI.getOperand(1)
+ .getFPImm()
+ ->getValueAPF()
+ .bitcastToAPInt()
+ .getZExtValue()));
+}
+
bool AArch64InstructionSelector::isLoadStoreOfNumBytes(
const MachineInstr &MI, unsigned NumBytes) const {
if (!MI.mayLoadOrStore())
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
new file mode 100644
index 0000000000000..4de2c934a672e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GISEL
+; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=FISEL
+
+; float foo(void) { return float(2147483648); }
+define float @select_fp_const() {
+; CHECK-LABEL: select_opt4
+; CHECK: movi v0.2s, #79, lsl #24
+; GISEL-LABEL: select_fp_const:
+; GISEL: // %bb.0: // %entry
+; GISEL-NEXT: movi v0.2s, #79, lsl #24
+; GISEL-NEXT: ret
+;
+; FISEL-LABEL: select_fp_const:
+; FISEL: // %bb.0: // %entry
+; FISEL-NEXT: adrp x8, .LCPI0_0
+; FISEL-NEXT: ldr s0, [x8, :lo12:.LCPI0_0]
+; FISEL-NEXT: ret
+entry:
+ ret float 0x41E0000000000000
+}
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