[PATCH] D122213: [RISCV] Enable MachineOutliner by default under -Oz for RISCV

Luís Marques via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 28 07:43:27 PDT 2022

Previous message: [llvm] a8c2770 - [NVPTX] Fix poorly designed assertion introduced in D120129
Next message: [PATCH] D122213: [RISCV] Enable MachineOutliner by default under -Oz for RISCV
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

luismarques added a comment.

It's probably a good idea to separate the fixes from the change to the default enable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122213/new/

https://reviews.llvm.org/D122213

Previous message: [llvm] a8c2770 - [NVPTX] Fix poorly designed assertion introduced in D120129
Next message: [PATCH] D122213: [RISCV] Enable MachineOutliner by default under -Oz for RISCV
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list