[PATCH] D122551: [AArch64] Enhance last active true vector combine

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14444-14445
 
-  // Restricted the DAG combine to only cases where we're extracting from a
-  // flag-setting operation
-  auto *CI = dyn_cast<ConstantSDNode>(Idx.getOperand(1));
-  if (!CI || !CI->isAllOnes() || SetCC.getOpcode() != ISD::SETCC)
+  // Last active extracting will output LASTB + WHILELS, and the WHILELS itself
+  // is a flag-setting operation, so perform it unconditionally.
+  if (!isAllOnesConstant(Idx.getOperand(1)))
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nit: this comment only makes sense compared to the previous code which had an explicit check for SETCC, so I think you can just remove this comment altogether.

Can you merge this condition with the condition above, e.g.:
```if (Idx.getOpcode() != ISD::ADD || !isAllOnesConstant(Idx.getOperand(1)))```


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  https://reviews.llvm.org/D122551/new/

https://reviews.llvm.org/D122551