[llvm] 4b28980 - [X86] Simplify the interface to getCondNoFromDesc.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-03-20T22:41:39-07:00
New Revision: 4b28980772402cab998e2c42e4876d6decb48583

URL: https://github.com/llvm/llvm-project/commit/4b28980772402cab998e2c42e4876d6decb48583
DIFF: https://github.com/llvm/llvm-project/commit/4b28980772402cab998e2c42e4876d6decb48583.diff

LOG: [X86] Simplify the interface to getCondNoFromDesc.

Instead of taking a SkipDefs parameter, rename to getCondSrcNoFromDesc
and have it return the source operand number. Make getCondFromMI
responsible for adding the number of Defs for MI instructions.

While there remove some unneeded casts to unsigned and check for
negative numbers instead of explicitly -1. Less than 0 is easier
for a compiler to codegen.

Differential Revision: https://reviews.llvm.org/D122113

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/lib/Target/X86/X86InstrInfo.cpp
    llvm/lib/Target/X86/X86InstrInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 8cdea8b60f3dd..aab534d2618c1 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2934,12 +2934,11 @@ X86::CondCode X86DAGToDAGISel::getCondFromNode(SDNode *N) const {
   assert(N->isMachineOpcode() && "Unexpected node");
   unsigned Opc = N->getMachineOpcode();
   const MCInstrDesc &MCID = getInstrInfo()->get(Opc);
-  int CondNo = X86::getCondNoFromDesc(MCID, /*SkipDefs=*/true);
-  if (CondNo == -1)
+  int CondNo = X86::getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
 
-  return static_cast<X86::CondCode>(
-      N->getConstantOperandVal(static_cast<unsigned>(CondNo)));
+  return static_cast<X86::CondCode>(N->getConstantOperandVal(CondNo));
 }
 
 /// Test whether the given X86ISD::CMP node has any users that use a flag

diff  --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 98ed40b8b4c21..705301e5d3610 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2584,26 +2584,22 @@ bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
   return false;
 }
 
-int X86::getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs) {
+int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
   unsigned Opcode = MCID.getOpcode();
   if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
     return -1;
-  unsigned NumOperands = MCID.getNumOperands();
-  unsigned NumDefs = MCID.getNumDefs();
-  // Assume that condition code is always the last operand
-  unsigned CondNo = NumOperands - 1;
-  if (SkipDefs)
-    return CondNo - NumDefs;
-  return CondNo;
+  // Assume that condition code is always the last use operand.
+  unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
+  return NumUses - 1;
 }
 
 X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
   const MCInstrDesc &MCID = MI.getDesc();
-  int CondNo = getCondNoFromDesc(MCID);
-  if (CondNo == -1)
+  int CondNo = getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
-  return static_cast<X86::CondCode>(
-      MI.getOperand(static_cast<unsigned>(CondNo)).getImm());
+  CondNo += MCID.getNumDefs();
+  return static_cast<X86::CondCode>(MI.getOperand(CondNo).getImm());
 }
 
 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {

diff  --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 902096940f1f0..92e14832aeded 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -40,12 +40,12 @@ std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
 
-/// Return the operand # for condition code by \p MCID. If
-/// the instruction doesn't have a condition code, return -1.
-int getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs = false);
+/// Return the source operand # for condition code by \p MCID. If the
+/// instruction doesn't have a condition code, return -1.
+int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
 
-/// Return the condition code of the instruction. If the instruction doesn't have a condition code,
-/// return X86::COND_INVALID.
+/// Return the condition code of the instruction. If the instruction doesn't
+/// have a condition code, return X86::COND_INVALID.
 CondCode getCondFromMI(const MachineInstr &MI);
 
 // Turn JCC instruction into condition code.