[PATCH] D122113: [X86] Simplify the interface to getCondNoFromDesc.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Instead of taking a SkipDefs parameter, rename to getCondSrcNoFromDesc
and have it return the source operand number. Make getCondFromMI
responsible for adding the number of Defs for MI instructions.

While there remove some unneeded casts to unsigned and check for
negative numbers instead of explicitly -1. Less than 0 is easier
for a compiler to codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122113

Files:
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h


Index: llvm/lib/Target/X86/X86InstrInfo.h
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.h
+++ llvm/lib/Target/X86/X86InstrInfo.h
@@ -40,12 +40,12 @@
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
 
-/// Return the operand # for condition code by \p MCID. If
-/// the instruction doesn't have a condition code, return -1.
-int getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs = false);
+/// Return the source operand # for condition code by \p MCID. If the
+/// instruction doesn't have a condition code, return -1.
+int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
 
-/// Return the condition code of the instruction. If the instruction doesn't have a condition code,
-/// return X86::COND_INVALID.
+/// Return the condition code of the instruction. If the instruction doesn't
+/// have a condition code, return X86::COND_INVALID.
 CondCode getCondFromMI(const MachineInstr &MI);
 
 // Turn JCC instruction into condition code.
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2584,26 +2584,21 @@
   return false;
 }
 
-int X86::getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs) {
+int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
   unsigned Opcode = MCID.getOpcode();
   if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
     return -1;
-  unsigned NumOperands = MCID.getNumOperands();
-  unsigned NumDefs = MCID.getNumDefs();
-  // Assume that condition code is always the last operand
-  unsigned CondNo = NumOperands - 1;
-  if (SkipDefs)
-    return CondNo - NumDefs;
-  return CondNo;
+  unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
+  return NumUses - 1;
 }
 
 X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
   const MCInstrDesc &MCID = MI.getDesc();
-  int CondNo = getCondNoFromDesc(MCID);
-  if (CondNo == -1)
+  int CondNo = getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
-  return static_cast<X86::CondCode>(
-      MI.getOperand(static_cast<unsigned>(CondNo)).getImm());
+  CondNo += MCID.getNumDefs();
+  return static_cast<X86::CondCode>(MI.getOperand(CondNo).getImm());
 }
 
 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2934,12 +2934,11 @@
   assert(N->isMachineOpcode() && "Unexpected node");
   unsigned Opc = N->getMachineOpcode();
   const MCInstrDesc &MCID = getInstrInfo()->get(Opc);
-  int CondNo = X86::getCondNoFromDesc(MCID, /*SkipDefs=*/true);
-  if (CondNo == -1)
+  int CondNo = X86::getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
 
-  return static_cast<X86::CondCode>(
-      N->getConstantOperandVal(static_cast<unsigned>(CondNo)));
+  return static_cast<X86::CondCode>(N->getConstantOperandVal(CondNo));
 }
 
 /// Test whether the given X86ISD::CMP node has any users that use a flag


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