[llvm] cb26730 - [X86][NFC] Unify implementations of getting condition code
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 20 20:32:50 PDT 2022
Author: Shengchen Kan
Date: 2022-03-21T11:31:16+08:00
New Revision: cb26730aaa8bba5c2ac627cf0e4a08a9ac388ef4
URL: https://github.com/llvm/llvm-project/commit/cb26730aaa8bba5c2ac627cf0e4a08a9ac388ef4
DIFF: https://github.com/llvm/llvm-project/commit/cb26730aaa8bba5c2ac627cf0e4a08a9ac388ef4.diff
LOG: [X86][NFC] Unify implementations of getting condition code
Added:
Modified:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index e9a1c304c2812..8cdea8b60f3dd 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -513,6 +513,9 @@ namespace {
return Subtarget->getInstrInfo();
}
+ /// Return a condition code of the given SDNode
+ X86::CondCode getCondFromNode(SDNode *N) const;
+
/// Address-mode matching performs shift-of-and to and-of-shift
/// reassociation in order to expose more scaled addressing
/// opportunities.
@@ -2927,24 +2930,16 @@ bool X86DAGToDAGISel::isSExtAbsoluteSymbolRef(unsigned Width, SDNode *N) const {
CR->getSignedMax().slt(1ull << Width);
}
-static X86::CondCode getCondFromNode(SDNode *N) {
+X86::CondCode X86DAGToDAGISel::getCondFromNode(SDNode *N) const {
assert(N->isMachineOpcode() && "Unexpected node");
- X86::CondCode CC = X86::COND_INVALID;
unsigned Opc = N->getMachineOpcode();
- if (Opc == X86::JCC_1)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(1));
- else if (Opc == X86::SETCCr)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(0));
- else if (Opc == X86::SETCCm)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(5));
- else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
- Opc == X86::CMOV64rr)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(2));
- else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
- Opc == X86::CMOV64rm)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(6));
-
- return CC;
+ const MCInstrDesc &MCID = getInstrInfo()->get(Opc);
+ int CondNo = X86::getCondNoFromDesc(MCID, /*SkipDefs=*/true);
+ if (CondNo == -1)
+ return X86::COND_INVALID;
+
+ return static_cast<X86::CondCode>(
+ N->getConstantOperandVal(static_cast<unsigned>(CondNo)));
}
/// Test whether the given X86ISD::CMP node has any users that use a flag
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5c70ad5da658f..13a52f9406617 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2584,34 +2584,39 @@ bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
return false;
}
-X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default: return X86::COND_INVALID;
- case X86::JCC_1:
+int X86::getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs) {
+ unsigned Opcode = MCID.getOpcode();
+ if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
+ return -1;
+ unsigned NumOperands = MCID.getNumOperands();
+ unsigned NumDefs = MCID.getNumDefs();
+ // Assume that condtion code is always the last operand
+ unsigned CondNo = NumOperands - 1;
+ if (SkipDefs)
+ return CondNo - NumDefs;
+ return CondNo;
+}
+
+X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
+ const MCInstrDesc &MCID = MI.getDesc();
+ int CondNo = getCondNoFromDesc(MCID);
+ if (CondNo == -1)
+ return X86::COND_INVALID;
+ else
return static_cast<X86::CondCode>(
- MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
- }
+ MI.getOperand(static_cast<unsigned>(CondNo)).getImm());
+}
+
+X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
+ return X86::isJCC(MI.getOpcode()) ? X86::getCondFromMI(MI) : X86::COND_INVALID;
}
-/// Return condition code of a SETCC opcode.
X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default: return X86::COND_INVALID;
- case X86::SETCCr: case X86::SETCCm:
- return static_cast<X86::CondCode>(
- MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
- }
+ return X86::isSETCC(MI.getOpcode()) ? X86::getCondFromMI(MI) : X86::COND_INVALID;
}
-/// Return condition code of a CMov opcode.
X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default: return X86::COND_INVALID;
- case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
- case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
- return static_cast<X86::CondCode>(
- MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
- }
+ return X86::isCMOVCC(MI.getOpcode()) ? X86::getCondFromMI(MI) : X86::COND_INVALID;
}
/// Return the inverse of the specified condition,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 9b0349668c1bb..902096940f1f0 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -40,13 +40,21 @@ std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
/// Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
-// Turn jCC instruction into condition code.
+/// Return the operand # for condition code by \p MCID. If
+/// the instruction doesn't have a condition code, return -1.
+int getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs = false);
+
+/// Return the condition code of the instruction. If the instruction doesn't have a condition code,
+/// return X86::COND_INVALID.
+CondCode getCondFromMI(const MachineInstr &MI);
+
+// Turn JCC instruction into condition code.
CondCode getCondFromBranch(const MachineInstr &MI);
-// Turn setCC instruction into condition code.
+// Turn SETCC instruction into condition code.
CondCode getCondFromSETCC(const MachineInstr &MI);
-// Turn CMov instruction into condition code.
+// Turn CMOV instruction into condition code.
CondCode getCondFromCMov(const MachineInstr &MI);
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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