[llvm] 34110a7 - [X86] combineAddOrSubToADCOrSBB - pull out repeated Y.getOperand(1) calls. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 19 11:00:40 PDT 2022
Author: Simon Pilgrim
Date: 2022-03-19T17:56:11Z
New Revision: 34110a73203d092f22dc1b2d1eae3ee758216b96
URL: https://github.com/llvm/llvm-project/commit/34110a73203d092f22dc1b2d1eae3ee758216b96
DIFF: https://github.com/llvm/llvm-project/commit/34110a73203d092f22dc1b2d1eae3ee758216b96.diff
LOG: [X86] combineAddOrSubToADCOrSBB - pull out repeated Y.getOperand(1) calls. NFC.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 242033bc6a5e6..c3a0a622ec073 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -52315,6 +52315,7 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
SDLoc DL(N);
EVT VT = N->getValueType(0);
X86::CondCode CC = (X86::CondCode)Y.getConstantOperandVal(0);
+ SDValue EFLAGS = Y.getOperand(1);
// If X is -1 or 0, then we have an opportunity to avoid constants required in
// the general case below.
@@ -52327,12 +52328,11 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
// 0 - SETB --> 0 - (CF) --> CF ? -1 : 0 --> SBB %eax, %eax
return DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
- Y.getOperand(1));
+ EFLAGS);
}
if ((!IsSub && CC == X86::COND_BE && ConstantX->isAllOnes()) ||
(IsSub && CC == X86::COND_A && ConstantX->isZero())) {
- SDValue EFLAGS = Y->getOperand(1);
if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
EFLAGS.getValueType().isInteger() &&
!isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
@@ -52355,11 +52355,10 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
// X - SETB Z --> sbb X, 0
return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
DAG.getVTList(VT, MVT::i32), X,
- DAG.getConstant(0, DL, VT), Y.getOperand(1));
+ DAG.getConstant(0, DL, VT), EFLAGS);
}
if (CC == X86::COND_A) {
- SDValue EFLAGS = Y.getOperand(1);
// Try to convert COND_A into COND_B in an attempt to facilitate
// materializing "setb reg".
//
@@ -52384,13 +52383,12 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
// X - SETAE --> adc X, -1
return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
DAG.getVTList(VT, MVT::i32), X,
- DAG.getConstant(-1, DL, VT), Y.getOperand(1));
+ DAG.getConstant(-1, DL, VT), EFLAGS);
}
if (CC == X86::COND_BE) {
// X + SETBE --> sbb X, -1
// X - SETBE --> adc X, -1
- SDValue EFLAGS = Y.getOperand(1);
// Try to convert COND_BE into COND_AE in an attempt to facilitate
// materializing "setae reg".
//
@@ -52413,13 +52411,12 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
if (CC != X86::COND_E && CC != X86::COND_NE)
return SDValue();
- SDValue Cmp = Y.getOperand(1);
- if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
- !X86::isZeroNode(Cmp.getOperand(1)) ||
- !Cmp.getOperand(0).getValueType().isInteger())
+ if (EFLAGS.getOpcode() != X86ISD::CMP || !EFLAGS.hasOneUse() ||
+ !X86::isZeroNode(EFLAGS.getOperand(1)) ||
+ !EFLAGS.getOperand(0).getValueType().isInteger())
return SDValue();
- SDValue Z = Cmp.getOperand(0);
+ SDValue Z = EFLAGS.getOperand(0);
EVT ZVT = Z.getValueType();
// If X is -1 or 0, then we have an opportunity to avoid constants required in
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