[llvm] d5fbcf7 - [VPlan] Improve pattern in vplan-printing.ll check line.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2022-03-19T16:03:25Z
New Revision: d5fbcf76fd9b0024fd452dd95c33f5ded042ba05

URL: https://github.com/llvm/llvm-project/commit/d5fbcf76fd9b0024fd452dd95c33f5ded042ba05
DIFF: https://github.com/llvm/llvm-project/commit/d5fbcf76fd9b0024fd452dd95c33f5ded042ba05.diff

LOG: [VPlan] Improve pattern in vplan-printing.ll check line.

The existing pattern only matched a single value, which breaks if the
numbering slightly changes.

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/vplan-printing.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
index a60c66d729363..afe7e6f20bc91 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -276,7 +276,7 @@ define float @print_fmuladd_strict(float* %a, float* %b, i64 %n) {
 ; CHECK-NEXT:   WIDEN ir<%l.a> = load ir<%arrayidx>
 ; CHECK-NEXT:   CLONE ir<%arrayidx2> = getelementptr ir<%b>, vp<[[STEPS]]>
 ; CHECK-NEXT:   WIDEN ir<%l.b> = load ir<%arrayidx2>
-; CHECK-NEXT:   EMIT vp<[[FMUL:%.]]> = fmul nnan ninf nsz ir<%l.a> ir<%l.b>
+; CHECK-NEXT:   EMIT vp<[[FMUL:%.+]]> = fmul nnan ninf nsz ir<%l.a> ir<%l.b>
 ; CHECK-NEXT:   REDUCE ir<[[MULADD:%.+]]> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<[[FMUL]]>)
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
 ; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>