[PATCH] D120648: [DAGCombine] fold (bswap(srl (bswap c), 8*x)) -> (shl c, 8*x)

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng added a comment.

In D120648#3389382 <https://reviews.llvm.org/D120648#3389382>, @spatel wrote:

> I didn't see a reply to my earlier suggestion - is there a problem with a more general pattern match (independent of the question of using knownbits on the shift amount)?
>
>   diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>   index 8e383ce85cb7..498d2f51bbd5 100644
>   --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>   +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>   @@ -9745,6 +9745,16 @@ SDValue DAGCombiner::visitBSWAP(SDNode *N) {
>        }
>      }
>    
>   +  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
>   +      N0.hasOneUse()) {
>   +    auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
>   +    if (ShAmt && ShAmt->getZExtValue() % 8 == 0) {
>   +      SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
>   +      unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
>   +      return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1));
>   +    }
>   +  }
>   +
>      return SDValue();
>    }

I thank this is a correct transform, it change bswap(shl x) -> srl (bswap x) or bswap(srl x) -> shl (bswap x)  and it may provide more opportunity for optimization;
but looking at this transformation alone, it doesn't do any optimization. Optimization needs to depend on other instructions before and after. Why don't we do accurate optimization?


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  https://reviews.llvm.org/D120648/new/

https://reviews.llvm.org/D120648